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Searched refs:DefIdx (Results 1 – 25 of 45) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
192 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
200 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
208 std::optional<unsigned> getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
214 std::optional<unsigned> DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
224 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
H A DMCSubtargetInfo.h177 unsigned DefIdx) const { in getWriteLatencyEntry() argument
178 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
181 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp146 unsigned DefIdx = 0; in findDefIdx() local
150 ++DefIdx; in findDefIdx()
152 return DefIdx; in findDefIdx()
202 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
203 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
206 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
228 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
H A DLiveIntervalCalc.cpp35 SlotIndex DefIdx = in createDeadDef() local
39 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
180 unsigned DefIdx; in extendToUses() local
183 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
186 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
H A DPeepholeOptimizer.cpp416 unsigned DefIdx = 0; member in __anon139b6b7f0111::ValueTracker
470 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1892 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1913 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1957 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
2001 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
2030 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
2126 assert(((Def->getOperand(DefIdx).isDef() && in getNextSourceImpl()
2127 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2129 Def->getOperand(DefIdx).isImplicit()) && in getNextSourceImpl()
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H A DTargetInstrInfo.cpp1393 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1457 unsigned DefIdx) const { in hasLowDefLatency()
1464 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1592 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1598 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1602 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
1619 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs() argument
1625 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1629 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def"); in getExtractSubregInputs()
1644 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs() argument
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H A DMachineVerifier.cpp2208 unsigned DefIdx; in visitMachineOperand() local
2212 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
2458 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
2468 !SlotIndex::isSameInstr(VNI->def, DefIdx) || in checkLivenessAtDef()
2469 (VNI->def != DefIdx && in checkLivenessAtDef()
2477 report_context(DefIdx); in checkLivenessAtDef()
2485 report_context(DefIdx); in checkLivenessAtDef()
2489 LiveQueryResult LRQ = LR.Query(DefIdx); in checkLivenessAtDef()
2656 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness() local
2657 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); in checkLiveness()
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H A DLiveRangeEdit.cpp167 SlotIndex DefIdx; in canRematerializeAt() local
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DMachineInstr.cpp277 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
278 if (DefIdx != -1) in addOperand()
279 tieOperands(DefIdx, OpNo); in addOperand()
919 unsigned DefIdx; in getRegClassConstraint() local
920 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
921 OpIdx = DefIdx; in getRegClassConstraint()
1121 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1122 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1129 if (DefIdx < TiedMax) in tieOperands()
1130 UseMO.TiedTo = DefIdx + 1; in tieOperands()
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp45 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
46 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
49 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h573 unsigned DefIdx = 0; in getDefIndex() local
577 ++DefIdx; in getDefIndex()
580 return DefIdx; in getDefIndex()
878 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeDefs() local
879 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs()
881 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
896 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
1136 ++j, ++DefIdx) in tryCombineUnmergeValues()
1183 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeValues() local
1416 unsigned DefIdx = 0) {
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h61 const MachineInstr &MI, unsigned DefIdx,
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
321 unsigned DefIdx,
325 SDNode *DefNode, unsigned DefIdx,
428 unsigned DefClass, unsigned DefIdx,
432 unsigned DefClass, unsigned DefIdx,
444 unsigned DefIdx, unsigned DefAlign,
451 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
466 const MachineInstr &DefMI, unsigned DefIdx,
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H A DARMBaseInstrInfo.cpp3879 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3882 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3919 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3922 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
4033 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
4148 DefIdx = Idx; in getBundledDefMI()
4369 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency()
4806 unsigned DefIdx, in hasHighOperandLatency() argument
4835 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
5452 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp623 int DefIdx = SwapMap[DefMI]; in formWebs() local
624 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
628 SwapVector[DefIdx].VSEId, in formWebs()
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
729 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
730 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
736 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
803 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
804 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
H A DPPCInstrInfo.h326 unsigned DefIdx,
330 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
333 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
339 unsigned DefIdx) const override { in hasLowDefLatency() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp399 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP() local
402 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers)) in handleADRP()
567 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
569 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
570 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
219 DefIdx != DefEnd; ++DefIdx) { in getLatency()
222 DefIdx); in getLatency()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h141 unsigned DefIdx = 0; variable
160 return DefIdx-1; in GetIdx()
H A DScheduleDAGSDNodes.cpp478 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
515 ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep); in AddSchedEdges()
578 DefIdx = 0; in InitNodeNumDefs()
592 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
593 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
595 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
596 ++DefIdx; in Advance()
658 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
663 TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h546 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
564 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
584 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1342 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1356 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1370 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1735 unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1747 const MachineInstr &DefMI, unsigned DefIdx,
1776 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1786 unsigned DefIdx) const;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp208 unsigned DefIdx = 0; in tryInlineAsm() local
212 if (Changed && Flag.isUseOperandTiedToDef(DefIdx)) in tryInlineAsm()
213 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
297 Flag.setMatchingOp(DefIdx); in tryInlineAsm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp162 unsigned DefIdx = 0; in selectInlineAsm() local
166 if (Changed && Flag.isUseOperandTiedToDef(DefIdx)) in selectInlineAsm()
167 IsTiedToChangedOp = OpChanged[DefIdx]; in selectInlineAsm()
252 Flag.setMatchingOp(DefIdx); in selectInlineAsm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp563 int DefIdx = -1; in restoreLatency() local
575 DefIdx = OpNum; in restoreLatency()
578 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
585 &InstrItins, *SrcI, DefIdx, *DstI, OpNum); in restoreLatency()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp383 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
386 for (unsigned i = 0; i < DefIdx; ++i) in lowerInlineAsm()
419 UseFlag.setMatchingOp(DefIdx); in lowerInlineAsm()

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