1383                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
1393     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
1395   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1457                                        unsigned DefIdx) const {  in hasLowDefLatency()
1464       ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1585     unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {  in getOperandLatency()  argument
1588   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1592     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1598     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1602   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1619     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1625     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1629   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1644     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1650     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1654   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()