3878                                   unsigned DefIdx, unsigned DefAlign) const {  in getVLDMDefCycle()  argument
3879   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;  in getVLDMDefCycle()
3882     return ItinData->getOperandCycle(DefClass, DefIdx);  in getVLDMDefCycle()
3918                                  unsigned DefIdx, unsigned DefAlign) const {  in getLDMDefCycle()  argument
3919   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;  in getLDMDefCycle()
3922     return ItinData->getOperandCycle(DefClass, DefIdx);  in getLDMDefCycle()
4018     unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID,  in getOperandLatency()  argument
4023   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())  in getOperandLatency()
4024     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
4033     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
4042     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4063     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4120     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,  in getOperandLatency()
4131                                            unsigned &DefIdx, unsigned &Dist) {  in getBundledDefMI()  argument
4148   DefIdx = Idx;  in getBundledDefMI()
4364     unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {  in getOperandLatency()  argument
4369   const MachineOperand &DefMO = DefMI.getOperand(DefIdx);  in getOperandLatency()
4376         getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);  in getOperandLatency()
4392       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,  in getOperandLatency()
4398     unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,  in getOperandLatencyImpl()  argument
4439       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);  in getOperandLatencyImpl()
4458                                     SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
4473         ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);  in getOperandLatency()
4489       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);  in getOperandLatency()
4520   } else if (DefIdx == 0 && Latency > 2U && Subtarget.isSwift()) {  in getOperandLatency()
4806                                              unsigned DefIdx,  in hasHighOperandLatency()  argument
4817       SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);  in hasHighOperandLatency()
4826                                         unsigned DefIdx) const {  in hasLowDefLatency()
4835         ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
5452     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceLikeInputs()  argument
5454   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getRegSequenceLikeInputs()
5479     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregLikeInputs()  argument
5481   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getExtractSubregLikeInputs()
5495     InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;  in getExtractSubregLikeInputs()
5502     const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,  in getInsertSubregLikeInputs()  argument
5504   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getInsertSubregLikeInputs()