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Searched refs:CPol (Results 1 – 15 of 15) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp279 AMDGPU::CPol::CPol Bit) const;
586 AMDGPU::CPol::CPol Value) const;
590 AMDGPU::CPol::CPol Value) const;
867 if (!CPol) in enableNamedBit()
870 CPol->setImm(CPol->getImm() | Bit); in enableNamedBit()
2167 if (!CPol) in setTH()
2171 if ((CPol->getImm() & AMDGPU::CPol::TH) != NewTH) { in setTH()
2172 CPol->setImm((CPol->getImm() & ~AMDGPU::CPol::TH) | NewTH); in setTH()
2182 if (!CPol) in setScope()
2187 CPol->setImm((CPol->getImm() & ~AMDGPU::CPol::SCOPE) | NewScope); in setScope()
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H A DMIMGInstructions.td448 Dim:$dim, UNorm:$unorm, CPol:$cpol,
461 Dim:$dim, UNorm:$unorm, CPol:$cpol,
473 Dim:$dim, UNorm:$unorm, CPol:$cpol,
486 Dim:$dim, UNorm:$unorm, CPol:$cpol,
702 Dim:$dim, UNorm:$unorm, CPol:$cpol,
728 Dim:$dim, UNorm:$unorm, CPol:$cpol,
858 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
870 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
919 Dim:$dim, UNorm:$unorm, CPol:$cpol,
947 Dim:$dim, UNorm:$unorm, CPol:$cpol,
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H A DSILoadStoreOptimizer.cpp117 unsigned CPol = 0; member
774 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
1005 if (CI.CPol != Paired.CPol) in offsetsCanBeCombined()
1427 New.addImm(CI.CPol).addMemOperand(combineKnownAdjacentMMOs(CI, Paired)); in mergeSMemLoadImmPair()
1480 .addImm(CI.CPol) // cpol in mergeBufferLoadPair()
1539 .addImm(CI.CPol) // cpol in mergeTBufferLoadPair()
1610 .addImm(CI.CPol) // cpol in mergeTBufferStorePair()
1638 .addImm(CI.CPol) in mergeFlatLoadPair()
1696 .addImm(CI.CPol) in mergeFlatStorePair()
1936 .addImm(CI.CPol) // cpol in mergeBufferStorePair()
H A DSIDefines.h355 namespace CPol {
357 enum CPol { enum
H A DSIInstrInfo.td854 ? AMDGPU::CPol::ALL
855 : AMDGPU::CPol::ALL_pregfx12),
862 ? AMDGPU::CPol::SWZ
863 : AMDGPU::CPol::SWZ_pregfx12);
869 ? AMDGPU::CPol::ALL
870 : AMDGPU::CPol::ALL_pregfx12);
1058 def CPol : CustomOperand<i32, 1>;
1059 def CPol_0 : DefaultOperand<CPol, 0>;
1060 def CPol_GLC1 : DefaultOperand<CPol, 1>;
1061 def CPol_GLC : ValuePredicatedOperand<CPol, "Op.getImm() & CPol::GLC">;
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H A DAMDGPUInstructionSelector.cpp1919 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in selectImageIntrinsic()
1920 if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) | in selectImageIntrinsic()
1921 AMDGPU::CPol::VOLATILE)) in selectImageIntrinsic()
2035 MIB.addImm(CPol); in selectImageIntrinsic()
3306 MIB.addImm(Aux & AMDGPU::CPol::ALL); // cpol in selectBufferLoadLds()
3307 MIB.addImm(Aux & AMDGPU::CPol::SWZ_pregfx12 ? 1 : 0); // swz in selectBufferLoadLds()
5710 (AMDGPU::isGFX12Plus(STI) ? AMDGPU::CPol::ALL in renderExtractCPol()
5711 : AMDGPU::CPol::ALL_pregfx12)); in renderExtractCPol()
5719 (AMDGPU::isGFX12Plus(STI) ? AMDGPU::CPol::SWZ in renderExtractSWZ()
5728 (AMDGPU::isGFX12Plus(STI) ? AMDGPU::CPol::ALL in renderExtractCpolSetGLC()
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H A DSMInstructions.td114 !con((ins baseClass:$sbase), offsets.Ins, (ins CPol:$cpol)),
130 offsets.Ins, (ins CPol:$cpol)),
486 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, CPol:$cpol);
769 let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, CPol:$cpol);
1404 let InOperandList = !con((ins BaseClass:$sbase), offsets.Ins, (ins CPol:$cpol));
H A DFLATInstructions.td210 !if(HasTiedOutput, (ins CPol:$cpol, vdata_op:$vdst_in),
321 (ins flat_offset:$offset, CPol:$cpol)),
341 FLAT_Pseudo<opName, (outs), (ins CPol:$cpol), "$cpol", [(node)]> {
389 !if(HasTiedOutput, (ins CPol:$cpol, getLdStRegisterOperand<regClass>.ret:$vdst_in),
470 (ins VGPR_32:$vaddr, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
472 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
474 (ins VGPR_32:$vaddr, flat_offset:$offset, CPol:$cpol),
475 (ins flat_offset:$offset, CPol:$cpol)))),
H A DSIISelLowering.cpp1187 if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE) in getTgtMemIntrinsic()
7728 unsigned CPol = cast<ConstantSDNode>( in lowerImage() local
7731 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in lowerImage()
7732 if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) | in lowerImage()
7733 AMDGPU::CPol::VOLATILE)) in lowerImage()
7755 Ops.push_back(DAG.getTargetConstant(CPol, DL, MVT::i32)); in lowerImage()
8122 unsigned CPol = Op.getConstantOperandVal(3); in LowerINTRINSIC_WO_CHAIN() local
8125 if (CPol & ~((Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12) in LowerINTRINSIC_WO_CHAIN()
8126 ? AMDGPU::CPol::ALL in LowerINTRINSIC_WO_CHAIN()
8127 : AMDGPU::CPol::ALL_pregfx12)) in LowerINTRINSIC_WO_CHAIN()
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H A DBUFInstructions.td667 (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, i1imm:$swz),
691 dag CPol = !if(vdata_in, (ins CPol_GLC_WithDefault:$cpol),
694 dag ret = !con(Data, MainInputs, CPol);
H A DSIRegisterInfo.cpp1664 MIB.addImm(LastUse ? AMDGPU::CPol::TH_LU : 0); // cpol in buildSpillLoadStore()
H A DSIInstrInfo.cpp6756 if (const MachineOperand *CPol = in legalizeOperands() local
6758 MIB.addImm(CPol->getImm()); in legalizeOperands()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp190 if (Imm & CPol::GLC) in printCPol()
194 if (Imm & CPol::SLC) in printCPol()
200 if (Imm & ~CPol::ALL) in printCPol()
240 case AMDGPU::CPol::TH_NT: in printTH()
243 case AMDGPU::CPol::TH_HT: in printTH()
250 case AMDGPU::CPol::TH_NT_RT: in printTH()
253 case AMDGPU::CPol::TH_RT_NT: in printTH()
256 case AMDGPU::CPol::TH_NT_HT: in printTH()
259 case AMDGPU::CPol::TH_NT_WB: in printTH()
270 if (Scope == CPol::SCOPE_CU) in printScope()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4748 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
4778 if (CPol & CPol::GLC) { in validateCoherencyBits()
4795 const unsigned TH = CPol & AMDGPU::CPol::TH; in validateTHAndScopeBits()
4796 const unsigned Scope = CPol & AMDGPU::CPol::SCOPE; in validateTHAndScopeBits()
4822 CPol & AMDGPU::CPol::TH_REAL_BYPASS) || in validateTHAndScopeBits()
4824 !(CPol & AMDGPU::CPol::TH_REAL_BYPASS))) in validateTHAndScopeBits()
4833 if (!(CPol & AMDGPU::CPol::TH_TYPE_ATOMIC)) in validateTHAndScopeBits()
4836 if (!(CPol & AMDGPU::CPol::TH_TYPE_STORE)) in validateTHAndScopeBits()
4839 if (!(CPol & AMDGPU::CPol::TH_TYPE_LOAD)) in validateTHAndScopeBits()
6342 if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC) in parseCPol()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp740 unsigned CPol = in getInstruction() local
742 AMDGPU::CPol::GLC : 0; in getInstruction()
744 insertNamedMCOperand(MI, MCOperand::createImm(CPol), in getInstruction()
746 } else if (CPol) { in getInstruction()
747 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); in getInstruction()