Lines Matching refs:CPol
1733 const unsigned CPol);
4736 unsigned CPol = Inst.getOperand(CPolPos).getImm(); in validateCoherencyBits() local
4739 return validateTHAndScopeBits(Inst, Operands, CPol); in validateCoherencyBits()
4743 if (CPol && (isSI() || isCI())) { in validateCoherencyBits()
4748 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
4754 if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) { in validateCoherencyBits()
4772 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
4778 if (CPol & CPol::GLC) { in validateCoherencyBits()
4794 const unsigned CPol) { in validateTHAndScopeBits() argument
4795 const unsigned TH = CPol & AMDGPU::CPol::TH; in validateTHAndScopeBits()
4796 const unsigned Scope = CPol & AMDGPU::CPol::SCOPE; in validateTHAndScopeBits()
4809 (!(TH & AMDGPU::CPol::TH_ATOMIC_RETURN))) in validateTHAndScopeBits()
4816 ((TH == AMDGPU::CPol::TH_NT_RT) || (TH == AMDGPU::CPol::TH_RT_NT) || in validateTHAndScopeBits()
4817 (TH == AMDGPU::CPol::TH_NT_HT))) in validateTHAndScopeBits()
4820 if (TH == AMDGPU::CPol::TH_BYPASS) { in validateTHAndScopeBits()
4821 if ((Scope != AMDGPU::CPol::SCOPE_SYS && in validateTHAndScopeBits()
4822 CPol & AMDGPU::CPol::TH_REAL_BYPASS) || in validateTHAndScopeBits()
4823 (Scope == AMDGPU::CPol::SCOPE_SYS && in validateTHAndScopeBits()
4824 !(CPol & AMDGPU::CPol::TH_REAL_BYPASS))) in validateTHAndScopeBits()
4833 if (!(CPol & AMDGPU::CPol::TH_TYPE_ATOMIC)) in validateTHAndScopeBits()
4836 if (!(CPol & AMDGPU::CPol::TH_TYPE_STORE)) in validateTHAndScopeBits()
4839 if (!(CPol & AMDGPU::CPol::TH_TYPE_LOAD)) in validateTHAndScopeBits()
6274 .Case("nt", AMDGPU::CPol::NT) in getCPolKind()
6275 .Case("sc0", AMDGPU::CPol::SC0) in getCPolKind()
6276 .Case("sc1", AMDGPU::CPol::SC1) in getCPolKind()
6281 .Case("dlc", AMDGPU::CPol::DLC) in getCPolKind()
6282 .Case("glc", AMDGPU::CPol::GLC) in getCPolKind()
6283 .Case("scc", AMDGPU::CPol::SCC) in getCPolKind()
6284 .Case("slc", AMDGPU::CPol::SLC) in getCPolKind()
6336 unsigned CPol = getCPolKind(getId(), Mnemo, Disabling); in parseCPol() local
6337 if (!CPol) in parseCPol()
6342 if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC) in parseCPol()
6345 if (!isGFX90A() && CPol == AMDGPU::CPol::SCC) in parseCPol()
6348 if (Seen & CPol) in parseCPol()
6352 Enabled |= CPol; in parseCPol()
6354 Seen |= CPol; in parseCPol()
6367 Scope = AMDGPU::CPol::SCOPE_CU; // default; in parseScope()
6378 .Case("SCOPE_CU", AMDGPU::CPol::SCOPE_CU) in parseScope()
6379 .Case("SCOPE_SE", AMDGPU::CPol::SCOPE_SE) in parseScope()
6380 .Case("SCOPE_DEV", AMDGPU::CPol::SCOPE_DEV) in parseScope()
6381 .Case("SCOPE_SYS", AMDGPU::CPol::SCOPE_SYS) in parseScope()
6391 TH = AMDGPU::CPol::TH_RT; // default in parseTH()
6400 TH = AMDGPU::CPol::TH_RT; in parseTH()
6406 TH = AMDGPU::CPol::TH_TYPE_ATOMIC; in parseTH()
6409 TH = AMDGPU::CPol::TH_TYPE_LOAD; in parseTH()
6412 TH = AMDGPU::CPol::TH_TYPE_STORE; in parseTH()
6418 TH |= AMDGPU::CPol::TH_REAL_BYPASS; in parseTH()
6421 if (TH & AMDGPU::CPol::TH_TYPE_ATOMIC) in parseTH()
6423 .Case("RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6424 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6425 .Case("RT_RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6426 .Case("NT", AMDGPU::CPol::TH_ATOMIC_NT) in parseTH()
6427 .Case("NT_RETURN", AMDGPU::CPol::TH_ATOMIC_NT | in parseTH()
6428 AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6429 .Case("CASCADE_RT", AMDGPU::CPol::TH_ATOMIC_CASCADE) in parseTH()
6430 .Case("CASCADE_NT", AMDGPU::CPol::TH_ATOMIC_CASCADE | in parseTH()
6431 AMDGPU::CPol::TH_ATOMIC_NT) in parseTH()
6435 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6436 .Case("NT", AMDGPU::CPol::TH_NT) in parseTH()
6437 .Case("HT", AMDGPU::CPol::TH_HT) in parseTH()
6438 .Case("LU", AMDGPU::CPol::TH_LU) in parseTH()
6439 .Case("RT_WB", AMDGPU::CPol::TH_RT_WB) in parseTH()
6440 .Case("NT_RT", AMDGPU::CPol::TH_NT_RT) in parseTH()
6441 .Case("RT_NT", AMDGPU::CPol::TH_RT_NT) in parseTH()
6442 .Case("NT_HT", AMDGPU::CPol::TH_NT_HT) in parseTH()
6443 .Case("NT_WB", AMDGPU::CPol::TH_NT_WB) in parseTH()
6444 .Case("BYPASS", AMDGPU::CPol::TH_BYPASS) in parseTH()
8028 IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC; in cvtMubufImpl()