| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | ARMTargetParser.def | 83 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
87 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
91 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
92 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
95 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
99 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
104 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
119 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
125 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
131 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1479 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1480 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV8()
1573 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1574 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV81()
2068 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves()
2281 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); in ExpandMI()
2314 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, in ExpandMI()
2315 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, in ExpandMI()
2316 ARM::R10, ARM::R11, ARM::R12}, in ExpandMI()
2521 ARM::t2BICri : ARM::BICri; in ExpandMI()
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| H A D | ARMFeatures.h | 28 case ARM::tADC: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
42 case ARM::tMUL: in isV8EligibleForIT()
43 case ARM::tMVN: in isV8EligibleForIT()
44 case ARM::tORR: in isV8EligibleForIT()
45 case ARM::tROR: in isV8EligibleForIT()
46 case ARM::tRSB: in isV8EligibleForIT()
47 case ARM::tSBC: in isV8EligibleForIT()
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| H A D | ARMFixCortexA57AES1742098Pass.cpp | 129 return Opc == ARM::AESD || Opc == ARM::AESE; in isFirstAESPairInstr()
145 case ARM::AESD: in isSafeAESInput()
146 case ARM::AESE: in isSafeAESInput()
147 case ARM::AESMC: in isSafeAESInput()
152 case ARM::VANDd: in isSafeAESInput()
153 case ARM::VANDq: in isSafeAESInput()
154 case ARM::VORRd: in isSafeAESInput()
155 case ARM::VORRq: in isSafeAESInput()
156 case ARM::VEORd: in isSafeAESInput()
157 case ARM::VEORq: in isSafeAESInput()
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| H A D | ARMRegisterBankInfo.cpp | 30 namespace ARM { namespace
242 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
243 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
264 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
278 ? &ARM::ValueMappings[ARM::GPR3OpsIdx] in getInstrMapping()
290 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
300 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
301 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; in getInstrMapping()
386 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
387 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
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| H A D | ARMBaseInstrInfo.cpp | 507 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
2422 {ARM::ADDSri, ARM::ADDri},
2423 {ARM::ADDSrr, ARM::ADDrr},
2424 {ARM::ADDSrsi, ARM::ADDrsi},
2425 {ARM::ADDSrsr, ARM::ADDrsr},
2427 {ARM::SUBSri, ARM::SUBri},
2428 {ARM::SUBSrr, ARM::SUBrr},
2432 {ARM::RSBSri, ARM::RSBri},
2439 {ARM::tADCS, ARM::tADC},
2444 {ARM::tSBCS, ARM::tSBC},
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| H A D | Thumb2SizeReduction.cpp | 85 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
86 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
119 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
121 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
132 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
141 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
151 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
263 case ARM::tMUL: in isHighLatencyCPSR()
391 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs()
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| H A D | Thumb2InstrInfo.cpp | 423 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
428 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
431 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
433 case ARM::t2PLIi12: return ARM::t2PLIi8; in negativeOffsetOpcode()
457 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
462 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
465 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
491 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
496 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
499 case ARM::t2PLDs: return ARM::t2PLDi12; in immediateOffsetOpcode()
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| H A D | ARMInstrInfo.cpp | 61 case ARM::LDRH_PRE: in getUnindexedOpcode()
62 case ARM::LDRH_POST: in getUnindexedOpcode()
63 return ARM::LDRH; in getUnindexedOpcode()
69 case ARM::LDRSH_PRE: in getUnindexedOpcode()
80 case ARM::STRH_PRE: in getUnindexedOpcode()
82 return ARM::STRH; in getUnindexedOpcode()
100 expandLoadStackGuardBase(MI, ARM::MRC, ARM::LDRi12); in expandLoadStackGuard()
112 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12); in expandLoadStackGuard()
114 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12); in expandLoadStackGuard()
119 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12); in expandLoadStackGuard()
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| H A D | ARMBaseInstrInfo.h | 567 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
643 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
647 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || in isJumpTableBranchOpcode()
648 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || in isJumpTableBranchOpcode()
654 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
720 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || in isPopOpcode()
725 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || in isPushOpcode()
731 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || in isSubImmOpcode()
732 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || in isSubImmOpcode()
733 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; in isSubImmOpcode()
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| H A D | ARMLoadStoreOptimizer.cpp | 501 Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; in UpdateBaseRegUses()
503 Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi; in UpdateBaseRegUses()
1039 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
1065 if (Reg == ARM::SP || Reg == ARM::PC) in FormCandidates()
1639 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1644 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1766 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1831 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1832 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1836 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
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| H A D | MVETailPredUtils.h | 30 case ARM::MVE_VCTP8: in VCTPOpcodeToLSTP()
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; in VCTPOpcodeToLSTP()
32 case ARM::MVE_VCTP16: in VCTPOpcodeToLSTP()
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; in VCTPOpcodeToLSTP()
34 case ARM::MVE_VCTP32: in VCTPOpcodeToLSTP()
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; in VCTPOpcodeToLSTP()
36 case ARM::MVE_VCTP64: in VCTPOpcodeToLSTP()
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; in VCTPOpcodeToLSTP()
46 case ARM::MVE_VCTP8: in getTailPredVectorWidth()
48 case ARM::MVE_VCTP16: in getTailPredVectorWidth()
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| H A D | ARMISelDAGToDAG.cpp | 3577 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
4269 unsigned Opc64[] = {ARM::VZIPd8, ARM::VZIPd16, ARM::VTRNd32}; in Select()
4270 unsigned Opc128[] = {ARM::VZIPq8, ARM::VZIPq16, ARM::VZIPq32}; in Select()
4281 unsigned Opc64[] = {ARM::VUZPd8, ARM::VUZPd16, ARM::VTRNd32}; in Select()
4282 unsigned Opc128[] = {ARM::VUZPq8, ARM::VUZPq16, ARM::VUZPq32}; in Select()
4292 unsigned Opc64[] = {ARM::VTRNd8, ARM::VTRNd16, ARM::VTRNd32}; in Select()
4293 unsigned Opc128[] = {ARM::VTRNq8, ARM::VTRNq16, ARM::VTRNq32}; in Select()
5282 ARM::MVE_VIDUPu8, ARM::MVE_VIDUPu16, ARM::MVE_VIDUPu32, in Select()
5292 ARM::MVE_VDDUPu8, ARM::MVE_VDDUPu16, ARM::MVE_VDDUPu32, in Select()
5302 ARM::MVE_VIWDUPu8, ARM::MVE_VIWDUPu16, ARM::MVE_VIWDUPu32, in Select()
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| H A D | ARMAsmPrinter.cpp | 1586 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction()
1774 case ARM::PICSTR: Opcode = ARM::STRrs; break; in emitInstruction()
1775 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; in emitInstruction()
1776 case ARM::PICSTRH: Opcode = ARM::STRH; break; in emitInstruction()
1777 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in emitInstruction()
1778 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; in emitInstruction()
1779 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in emitInstruction()
1780 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in emitInstruction()
1781 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in emitInstruction()
1842 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in emitInstruction()
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| H A D | ARMFrameLowering.cpp | 2377 case ARM::R0: case ARM::R1: in determineCalleeSaves()
2378 case ARM::R2: case ARM::R3: in determineCalleeSaves()
2379 case ARM::R4: case ARM::R5: in determineCalleeSaves()
2380 case ARM::R6: case ARM::R7: in determineCalleeSaves()
2393 case ARM::R0: case ARM::R1: in determineCalleeSaves()
2394 case ARM::R2: case ARM::R3: in determineCalleeSaves()
2395 case ARM::R4: case ARM::R5: in determineCalleeSaves()
2396 case ARM::R6: case ARM::R7: in determineCalleeSaves()
2568 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { in determineCalleeSaves()
2589 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
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| H A D | ARMTargetTransformInfo.h | 73 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
74 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
75 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
76 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
78 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
79 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
80 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
92 ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
93 ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
94 ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
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| H A D | Thumb1FrameLowering.cpp | 90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
458 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
462 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4) in emitPrologue()
468 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4) in emitPrologue()
474 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
562 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
567 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
838 static const SmallVector<Register> OrderedLowRegs = {ARM::R4, ARM::R5, ARM::R6,
843 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
844 ARM::R5, ARM::R6, ARM::R7, ARM::LR};
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| H A D | ARMCallingConv.cpp | 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
156 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
157 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
158 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
159 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
160 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | ARMTargetParser.cpp | 31 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
154 bool ARM::getFPUFeatures(ARM::FPUKind FPUKind, in getFPUFeatures()
219 ARM::FPUKind ARM::parseFPU(StringRef FPU) { in parseFPU()
228 ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(ARM::FPUKind FPUKind) { in getFPUNeonSupportLevel()
257 ARM::FPUVersion ARM::getFPUVersion(ARM::FPUKind FPUKind) { in getFPUVersion()
263 ARM::FPURestriction ARM::getFPURestriction(ARM::FPUKind FPUKind) { in getFPURestriction()
269 ARM::FPUKind ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) { in getDefaultFPU()
332 StringRef ARM::getCPUAttr(ARM::ArchKind AK) { in getCPUAttr()
336 StringRef ARM::getSubArch(ARM::ArchKind AK) { in getSubArch()
340 unsigned ARM::getArchAttr(ARM::ArchKind AK) { in getArchAttr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMTargetStreamer.cpp | 146 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
188 emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM); in emitTargetAttributes()
232 emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16 in emitTargetAttributes()
247 emitFPU(STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16 in emitTargetAttributes()
250 emitArchExtension(ARM::AEK_SIMD | ARM::AEK_DSP | ARM::AEK_FP); in emitTargetAttributes()
255 : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_VFPV4_D16 in emitTargetAttributes()
261 ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16 in emitTargetAttributes()
268 : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16 in emitTargetAttributes()
271 emitFPU(ARM::FK_VFPV2); in emitTargetAttributes()
275 if (STI.hasFeature(ARM::FeatureVFP2_SP) && !STI.hasFeature(ARM::FeatureFP64)) in emitTargetAttributes()
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| H A D | ARMAsmBackend.cpp | 231 case ARM::tBcc: in getRelaxedOpcode()
233 case ARM::tLDRpci: in getRelaxedOpcode()
235 case ARM::tADR: in getRelaxedOpcode()
237 case ARM::tB: in getRelaxedOpcode()
239 case ARM::tCBZ: in getRelaxedOpcode()
240 return ARM::tHINT; in getRelaxedOpcode()
241 case ARM::tCBNZ: in getRelaxedOpcode()
242 return ARM::tHINT; in getRelaxedOpcode()
315 case ARM::fixup_wls: in reasonForFixupRelaxation()
317 case ARM::fixup_le: in reasonForFixupRelaxation()
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| H A D | ARMMCTargetDesc.cpp | 40 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMCRDeprecationInfo()
67 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMCRDeprecationInfo()
79 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMRCDeprecationInfo()
117 case ARM::LR: in getARMLoadDeprecationInfo()
120 case ARM::PC: in getARMLoadDeprecationInfo()
144 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); in ParseARMTriple()
198 if (InstDesc.getOpcode() == ARM::tBLXi) in evaluateBranchTarget()
229 {codeview::RegisterId::ARM_R0, ARM::R0}, in initLLVMToCVRegMapping()
230 {codeview::RegisterId::ARM_R1, ARM::R1}, in initLLVMToCVRegMapping()
231 {codeview::RegisterId::ARM_R2, ARM::R2}, in initLLVMToCVRegMapping()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1280 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1281 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1282 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1283 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1287 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1288 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1289 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1588 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1589 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1590 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 4425 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
4426 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
4427 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
4428 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
4429 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
4430 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
4431 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
4432 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
12641 {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12644 {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
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| /freebsd-14.2/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | ARM.cpp | 119 llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName); in setArchInfo()
143 (ArchISA == llvm::ARM::ISAKind::ARM && ArchVersion >= 6) || in setAtomic()
245 case llvm::ARM::ProfileKind::A: in getCPUProfile()
386 llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(Arch); in isBranchProtectionSupportedArch()
399 llvm::ARM::ProfileKind Profile = llvm::ARM::parseArchProfile(SubArch); in isBranchProtectionSupportedArch()
436 llvm::ARM::ArchKind Arch = llvm::ARM::parseArch(getTriple().getArchName()); in initFeatureMap()
440 llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(CPU); in initFeatureMap()
451 for (llvm::ARM::ArchKind I = llvm::ARM::convertV9toV8(CPUArch); in initFeatureMap()
456 for (llvm::ARM::ArchKind I = CPUArch; I != llvm::ARM::ArchKind::INVALID; in initFeatureMap()
462 llvm::ARM::FPUKind FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); in initFeatureMap()
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