Lines Matching refs:ARM
124 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
180 FPReg = ARM::SP; in reset()
304 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
361 return MRI->getSubReg(QReg, ARM::dsub_0); in getDRegFromQReg()
524 return getSTI().hasFeature(ARM::ModeThumb); in isThumb()
528 return isThumb() && !getSTI().hasFeature(ARM::FeatureThumb2); in isThumbOne()
532 return isThumb() && getSTI().hasFeature(ARM::FeatureThumb2); in isThumbTwo()
536 return getSTI().hasFeature(ARM::HasV4TOps); in hasThumb()
540 return getSTI().hasFeature(ARM::FeatureThumb2); in hasThumb2()
544 return getSTI().hasFeature(ARM::HasV6Ops); in hasV6Ops()
548 return getSTI().hasFeature(ARM::HasV6T2Ops); in hasV6T2Ops()
552 return getSTI().hasFeature(ARM::HasV6MOps); in hasV6MOps()
556 return getSTI().hasFeature(ARM::HasV7Ops); in hasV7Ops()
560 return getSTI().hasFeature(ARM::HasV8Ops); in hasV8Ops()
564 return getSTI().hasFeature(ARM::HasV8MBaselineOps); in hasV8MBaseline()
568 return getSTI().hasFeature(ARM::HasV8MMainlineOps); in hasV8MMainline()
571 return getSTI().hasFeature(ARM::HasV8_1MMainlineOps); in hasV8_1MMainline()
574 return getSTI().hasFeature(ARM::HasMVEIntegerOps); in hasMVE()
577 return getSTI().hasFeature(ARM::HasMVEFloatOps); in hasMVEFloat()
580 return getSTI().hasFeature(ARM::HasCDEOps); in hasCDE()
583 return getSTI().hasFeature(ARM::Feature8MSecExt); in has8MSecExt()
587 return !getSTI().hasFeature(ARM::FeatureNoARM); in hasARM()
591 return getSTI().hasFeature(ARM::FeatureDSP); in hasDSP()
595 return getSTI().hasFeature(ARM::FeatureD32); in hasD32()
599 return getSTI().hasFeature(ARM::HasV8_1aOps); in hasV8_1aOps()
603 return getSTI().hasFeature(ARM::FeatureRAS); in hasRAS()
608 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); in SwitchMode()
615 return getSTI().hasFeature(ARM::FeatureMClass); in isMClass()
1122 if(Memory.BaseRegNum != ARM::PC) return false; in isThumbMemPC()
1360 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && in isMVEMem()
1361 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) in isMVEMem()
1364 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMVEMem()
1373 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) in isGPRMem()
1376 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) in isGPRMem()
1383 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1385 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1390 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedImm()
1443 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); in isPostIdxRegShifted()
1459 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemNoOffsetT2()
1471 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( in isMemNoOffsetT2NoSp()
1483 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( in isMemNoOffsetT()
1495 if (Memory.BaseRegNum != ARM::PC) in isMemPCRelImm12()
1702 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) in isT2MemRegOffset()
1763 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) in isMemThumbSPI()
1800 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemImm7s4Offset()
1829 if (Memory.BaseRegNum == ARM::PC) return false; in isMemImm8Offset()
1875 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemRegRQOffset()
1878 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMemRegRQOffset()
1896 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMemRegQOffset()
1936 if (Memory.BaseRegNum == ARM::PC) return false; in isMemNegImm8Offset()
2025 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isVecListTwoMQ()
2031 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPair()
2048 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] in isVecListDPairSpaced()
2064 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isVecListFourMQ()
2083 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPairAllLanes()
2473 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2480 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; in addVPTPredNOperands()
2494 ARMDescs.Insts[ARM::INSTRUCTION_LIST_END - 1 - Inst.getOpcode()]; in addVPTPredROperands()
3349 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; in addMVEVecListOperands()
3351 (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID] in addMVEVecListOperands()
3352 : &ARMMCRegisterClasses[ARM::MQQQQPRRegClassID]; in addMVEVecListOperands()
3446 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONi8ReplicateOperands()
3447 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONi8ReplicateOperands()
3489 assert((Inst.getOpcode() == ARM::VMOVv4i16 || in addNEONvmovi16ReplicateOperands()
3490 Inst.getOpcode() == ARM::VMOVv8i16 || in addNEONvmovi16ReplicateOperands()
3491 Inst.getOpcode() == ARM::VMVNv4i16 || in addNEONvmovi16ReplicateOperands()
3492 Inst.getOpcode() == ARM::VMVNv8i16) && in addNEONvmovi16ReplicateOperands()
3513 assert((Inst.getOpcode() == ARM::VMOVv2i32 || in addNEONvmovi32ReplicateOperands()
3514 Inst.getOpcode() == ARM::VMOVv4i32 || in addNEONvmovi32ReplicateOperands()
3515 Inst.getOpcode() == ARM::VMVNv2i32 || in addNEONvmovi32ReplicateOperands()
3516 Inst.getOpcode() == ARM::VMVNv4i32) && in addNEONvmovi32ReplicateOperands()
3715 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in CreateRegList()
3717 if (Regs.back().second == ARM::VPR) in CreateRegList()
3721 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( in CreateRegList()
3723 if (Regs.back().second == ARM::VPR) in CreateRegList()
3729 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) in CreateRegList()
4081 .Case("r13", ARM::SP) in tryParseRegister()
4082 .Case("r14", ARM::LR) in tryParseRegister()
4083 .Case("r15", ARM::PC) in tryParseRegister()
4084 .Case("ip", ARM::R12) in tryParseRegister()
4086 .Case("a1", ARM::R0) in tryParseRegister()
4087 .Case("a2", ARM::R1) in tryParseRegister()
4088 .Case("a3", ARM::R2) in tryParseRegister()
4089 .Case("a4", ARM::R3) in tryParseRegister()
4090 .Case("v1", ARM::R4) in tryParseRegister()
4091 .Case("v2", ARM::R5) in tryParseRegister()
4092 .Case("v3", ARM::R6) in tryParseRegister()
4093 .Case("v4", ARM::R7) in tryParseRegister()
4094 .Case("v5", ARM::R8) in tryParseRegister()
4095 .Case("v6", ARM::R9) in tryParseRegister()
4096 .Case("v7", ARM::R10) in tryParseRegister()
4097 .Case("v8", ARM::R11) in tryParseRegister()
4098 .Case("sb", ARM::R9) in tryParseRegister()
4099 .Case("sl", ARM::R10) in tryParseRegister()
4100 .Case("fp", ARM::R11) in tryParseRegister()
4116 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31) in tryParseRegister()
4421 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in getNextRegister()
4425 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
4426 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
4427 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
4428 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
4429 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
4430 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
4431 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
4432 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
4469 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE) in parseRegisterList()
4477 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
4484 if (Reg == ARM::RA_AUTH_CODE || in parseRegisterList()
4485 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
4486 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; in parseRegisterList()
4487 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) in parseRegisterList()
4488 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; in parseRegisterList()
4489 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) in parseRegisterList()
4490 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; in parseRegisterList()
4491 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) in parseRegisterList()
4492 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; in parseRegisterList()
4506 if (Reg == ARM::RA_AUTH_CODE) in parseRegisterList()
4513 if (EndReg == ARM::RA_AUTH_CODE) in parseRegisterList()
4516 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseRegisterList()
4548 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE) in parseRegisterList()
4552 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
4556 if (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg) && in parseRegisterList()
4557 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() && in parseRegisterList()
4558 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) { in parseRegisterList()
4561 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; in parseRegisterList()
4563 if (Reg == ARM::VPR && in parseRegisterList()
4564 (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || in parseRegisterList()
4565 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] || in parseRegisterList()
4566 RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) { in parseRegisterList()
4567 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; in parseRegisterList()
4576 if ((Reg == ARM::RA_AUTH_CODE && in parseRegisterList()
4577 RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) || in parseRegisterList()
4578 (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg))) in parseRegisterList()
4586 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
4588 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) in parseRegisterList()
4592 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && in parseRegisterList()
4593 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && in parseRegisterList()
4682 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { in parseVectorList()
4702 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4709 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
4710 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
4714 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
4715 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
4743 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) in parseVectorList()
4748 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4774 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseVectorList()
4782 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || in parseVectorList()
4784 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) in parseVectorList()
4810 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) in parseVectorList()
4820 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4874 &ARMMCRegisterClasses[ARM::DPairRegClassID] : in parseVectorList()
4875 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; in parseVectorList()
4876 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
5620 case ARM::tB: in cvtThumbBranches()
5621 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; in cvtThumbBranches()
5623 case ARM::t2B: in cvtThumbBranches()
5624 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; in cvtThumbBranches()
5634 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
5635 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
5642 case ARM::tB: in cvtThumbBranches()
5643 case ARM::tBcc: in cvtThumbBranches()
5644 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
5646 case ARM::t2B: in cvtThumbBranches()
5647 case ARM::t2Bcc: in cvtThumbBranches()
5648 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
5656 case ARM::tB: { in cvtThumbBranches()
5659 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
5663 case ARM::tBcc: { in cvtThumbBranches()
5666 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
6513 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || in tryConvertingToTwoOperandForm()
6514 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
6516 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || in tryConvertingToTwoOperandForm()
6517 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
6518 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && in tryConvertingToTwoOperandForm()
6543 ((Mnemonic == "add" && Op4Reg != ARM::SP) || in tryConvertingToTwoOperandForm()
6632 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6657 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6710 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6726 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP && in shouldOmitCCOutOperand()
6727 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6759 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in shouldOmitPredicateOperand()
6761 ARMMCRegisterClasses[ARM::QPRRegClassID].contains( in shouldOmitPredicateOperand()
6786 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6788 ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6801 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6852 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()
6862 if (Op2.getReg() == ARM::PC) in fixupGNULDRDAlias()
6865 if (!PairedReg || PairedReg == ARM::PC || in fixupGNULDRDAlias()
6866 (PairedReg == ARM::SP && !hasV8Ops())) in fixupGNULDRDAlias()
6901 case ARM::R0: in CDEConvertDualRegOperand()
6902 RNext = ARM::R1; in CDEConvertDualRegOperand()
6903 RPair = ARM::R0_R1; in CDEConvertDualRegOperand()
6905 case ARM::R2: in CDEConvertDualRegOperand()
6906 RNext = ARM::R3; in CDEConvertDualRegOperand()
6907 RPair = ARM::R2_R3; in CDEConvertDualRegOperand()
6909 case ARM::R4: in CDEConvertDualRegOperand()
6910 RNext = ARM::R5; in CDEConvertDualRegOperand()
6911 RPair = ARM::R4_R5; in CDEConvertDualRegOperand()
6913 case ARM::R6: in CDEConvertDualRegOperand()
6914 RNext = ARM::R7; in CDEConvertDualRegOperand()
6915 RPair = ARM::R6_R7; in CDEConvertDualRegOperand()
6917 case ARM::R8: in CDEConvertDualRegOperand()
6918 RNext = ARM::R9; in CDEConvertDualRegOperand()
6919 RPair = ARM::R8_R9; in CDEConvertDualRegOperand()
6921 case ARM::R10: in CDEConvertDualRegOperand()
6922 RNext = ARM::R11; in CDEConvertDualRegOperand()
6923 RPair = ARM::R10_R11; in CDEConvertDualRegOperand()
7051 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
7309 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
7325 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID))); in ParseInstruction()
7342 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
7344 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
7386 return Inst.getOpcode() == ARM::tBKPT || in instIsBreakpoint()
7387 Inst.getOpcode() == ARM::BKPT || in instIsBreakpoint()
7388 Inst.getOpcode() == ARM::tHLT || in instIsBreakpoint()
7389 Inst.getOpcode() == ARM::HLT; in instIsBreakpoint()
7398 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetLDMRegList()
7399 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); in validatetLDMRegList()
7400 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetLDMRegList()
7417 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetSTMRegList()
7418 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetSTMRegList()
7492 if (ARM::isVpred(MCID.operands()[i].OperandType)) in findFirstVectorPredOperandIdx()
7544 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && in validateInstruction()
7545 Inst.getOpcode() != ARM::t2Bcc && in validateInstruction()
7546 Inst.getOpcode() != ARM::t2BFic) { in validateInstruction()
7596 case ARM::t2IT: { in validateInstruction()
7610 case ARM::LDRD: in validateInstruction()
7615 case ARM::LDRD_PRE: in validateInstruction()
7616 case ARM::LDRD_POST: in validateInstruction()
7621 case ARM::t2LDRDi8: in validateInstruction()
7626 case ARM::t2LDRD_PRE: in validateInstruction()
7627 case ARM::t2LDRD_POST: in validateInstruction()
7632 case ARM::t2BXJ: { in validateInstruction()
7635 if (RmReg == ARM::SP && !hasV8Ops()) in validateInstruction()
7640 case ARM::STRD: in validateInstruction()
7645 case ARM::STRD_PRE: in validateInstruction()
7646 case ARM::STRD_POST: in validateInstruction()
7651 case ARM::t2STRD_PRE: in validateInstruction()
7652 case ARM::t2STRD_POST: in validateInstruction()
7657 case ARM::STR_PRE_IMM: in validateInstruction()
7658 case ARM::STR_PRE_REG: in validateInstruction()
7659 case ARM::t2STR_PRE: in validateInstruction()
7660 case ARM::STR_POST_IMM: in validateInstruction()
7661 case ARM::STR_POST_REG: in validateInstruction()
7662 case ARM::t2STR_POST: in validateInstruction()
7663 case ARM::STRH_PRE: in validateInstruction()
7664 case ARM::t2STRH_PRE: in validateInstruction()
7665 case ARM::STRH_POST: in validateInstruction()
7666 case ARM::t2STRH_POST: in validateInstruction()
7667 case ARM::STRB_PRE_IMM: in validateInstruction()
7668 case ARM::STRB_PRE_REG: in validateInstruction()
7669 case ARM::t2STRB_PRE: in validateInstruction()
7670 case ARM::STRB_POST_IMM: in validateInstruction()
7671 case ARM::STRB_POST_REG: in validateInstruction()
7672 case ARM::t2STRB_POST: { in validateInstruction()
7682 case ARM::t2LDR_PRE_imm: in validateInstruction()
7683 case ARM::t2LDR_POST_imm: in validateInstruction()
7684 case ARM::t2STR_PRE_imm: in validateInstruction()
7685 case ARM::t2STR_POST_imm: { in validateInstruction()
7693 if (Inst.getOpcode() == ARM::t2LDR_POST_imm || in validateInstruction()
7694 Inst.getOpcode() == ARM::t2STR_POST_imm) { in validateInstruction()
7700 if (Inst.getOpcode() == ARM::t2STR_PRE_imm || in validateInstruction()
7701 Inst.getOpcode() == ARM::t2STR_POST_imm) { in validateInstruction()
7702 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7710 case ARM::t2LDRB_OFFSET_imm: in validateInstruction()
7711 case ARM::t2LDRB_PRE_imm: in validateInstruction()
7712 case ARM::t2LDRB_POST_imm: in validateInstruction()
7713 case ARM::t2STRB_OFFSET_imm: in validateInstruction()
7714 case ARM::t2STRB_PRE_imm: in validateInstruction()
7715 case ARM::t2STRB_POST_imm: { in validateInstruction()
7716 if (Inst.getOpcode() == ARM::t2LDRB_POST_imm || in validateInstruction()
7717 Inst.getOpcode() == ARM::t2STRB_POST_imm || in validateInstruction()
7718 Inst.getOpcode() == ARM::t2LDRB_PRE_imm || in validateInstruction()
7719 Inst.getOpcode() == ARM::t2STRB_PRE_imm) { in validateInstruction()
7724 } else if (Inst.getOpcode() == ARM::t2LDRB_OFFSET_imm || in validateInstruction()
7725 Inst.getOpcode() == ARM::t2STRB_OFFSET_imm) { in validateInstruction()
7731 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7738 case ARM::t2LDRH_OFFSET_imm: in validateInstruction()
7739 case ARM::t2LDRH_PRE_imm: in validateInstruction()
7740 case ARM::t2LDRH_POST_imm: in validateInstruction()
7741 case ARM::t2STRH_OFFSET_imm: in validateInstruction()
7742 case ARM::t2STRH_PRE_imm: in validateInstruction()
7743 case ARM::t2STRH_POST_imm: { in validateInstruction()
7744 if (Inst.getOpcode() == ARM::t2LDRH_POST_imm || in validateInstruction()
7745 Inst.getOpcode() == ARM::t2STRH_POST_imm || in validateInstruction()
7746 Inst.getOpcode() == ARM::t2LDRH_PRE_imm || in validateInstruction()
7747 Inst.getOpcode() == ARM::t2STRH_PRE_imm) { in validateInstruction()
7752 } else if (Inst.getOpcode() == ARM::t2LDRH_OFFSET_imm || in validateInstruction()
7753 Inst.getOpcode() == ARM::t2STRH_OFFSET_imm) { in validateInstruction()
7759 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7766 case ARM::t2LDRSB_OFFSET_imm: in validateInstruction()
7767 case ARM::t2LDRSB_PRE_imm: in validateInstruction()
7768 case ARM::t2LDRSB_POST_imm: { in validateInstruction()
7769 if (Inst.getOpcode() == ARM::t2LDRSB_POST_imm || in validateInstruction()
7770 Inst.getOpcode() == ARM::t2LDRSB_PRE_imm) { in validateInstruction()
7775 } else if (Inst.getOpcode() == ARM::t2LDRSB_OFFSET_imm) { in validateInstruction()
7781 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7788 case ARM::t2LDRSH_OFFSET_imm: in validateInstruction()
7789 case ARM::t2LDRSH_PRE_imm: in validateInstruction()
7790 case ARM::t2LDRSH_POST_imm: { in validateInstruction()
7791 if (Inst.getOpcode() == ARM::t2LDRSH_POST_imm || in validateInstruction()
7792 Inst.getOpcode() == ARM::t2LDRSH_PRE_imm) { in validateInstruction()
7797 } else if (Inst.getOpcode() == ARM::t2LDRSH_OFFSET_imm) { in validateInstruction()
7803 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7810 case ARM::LDR_PRE_IMM: in validateInstruction()
7811 case ARM::LDR_PRE_REG: in validateInstruction()
7812 case ARM::t2LDR_PRE: in validateInstruction()
7813 case ARM::LDR_POST_IMM: in validateInstruction()
7814 case ARM::LDR_POST_REG: in validateInstruction()
7815 case ARM::t2LDR_POST: in validateInstruction()
7816 case ARM::LDRH_PRE: in validateInstruction()
7817 case ARM::t2LDRH_PRE: in validateInstruction()
7818 case ARM::LDRH_POST: in validateInstruction()
7819 case ARM::t2LDRH_POST: in validateInstruction()
7820 case ARM::LDRSH_PRE: in validateInstruction()
7821 case ARM::t2LDRSH_PRE: in validateInstruction()
7822 case ARM::LDRSH_POST: in validateInstruction()
7823 case ARM::t2LDRSH_POST: in validateInstruction()
7824 case ARM::LDRB_PRE_IMM: in validateInstruction()
7825 case ARM::LDRB_PRE_REG: in validateInstruction()
7826 case ARM::t2LDRB_PRE: in validateInstruction()
7827 case ARM::LDRB_POST_IMM: in validateInstruction()
7828 case ARM::LDRB_POST_REG: in validateInstruction()
7829 case ARM::t2LDRB_POST: in validateInstruction()
7830 case ARM::LDRSB_PRE: in validateInstruction()
7831 case ARM::t2LDRSB_PRE: in validateInstruction()
7832 case ARM::LDRSB_POST: in validateInstruction()
7833 case ARM::t2LDRSB_POST: { in validateInstruction()
7844 case ARM::MVE_VLDRBU8_rq: in validateInstruction()
7845 case ARM::MVE_VLDRBU16_rq: in validateInstruction()
7846 case ARM::MVE_VLDRBS16_rq: in validateInstruction()
7847 case ARM::MVE_VLDRBU32_rq: in validateInstruction()
7848 case ARM::MVE_VLDRBS32_rq: in validateInstruction()
7849 case ARM::MVE_VLDRHU16_rq: in validateInstruction()
7850 case ARM::MVE_VLDRHU16_rq_u: in validateInstruction()
7851 case ARM::MVE_VLDRHU32_rq: in validateInstruction()
7852 case ARM::MVE_VLDRHU32_rq_u: in validateInstruction()
7853 case ARM::MVE_VLDRHS32_rq: in validateInstruction()
7854 case ARM::MVE_VLDRHS32_rq_u: in validateInstruction()
7855 case ARM::MVE_VLDRWU32_rq: in validateInstruction()
7856 case ARM::MVE_VLDRWU32_rq_u: in validateInstruction()
7857 case ARM::MVE_VLDRDU64_rq: in validateInstruction()
7858 case ARM::MVE_VLDRDU64_rq_u: in validateInstruction()
7859 case ARM::MVE_VLDRWU32_qi: in validateInstruction()
7860 case ARM::MVE_VLDRWU32_qi_pre: in validateInstruction()
7861 case ARM::MVE_VLDRDU64_qi: in validateInstruction()
7862 case ARM::MVE_VLDRDU64_qi_pre: { in validateInstruction()
7867 case ARM::MVE_VLDRWU32_qi: in validateInstruction()
7868 case ARM::MVE_VLDRDU64_qi: in validateInstruction()
7872 case ARM::MVE_VLDRWU32_qi_pre: in validateInstruction()
7873 case ARM::MVE_VLDRDU64_qi_pre: in validateInstruction()
7891 case ARM::SBFX: in validateInstruction()
7892 case ARM::t2SBFX: in validateInstruction()
7893 case ARM::UBFX: in validateInstruction()
7894 case ARM::t2UBFX: { in validateInstruction()
7904 case ARM::tLDMIA: { in validateInstruction()
7934 case ARM::LDMIA_UPD: in validateInstruction()
7935 case ARM::LDMDB_UPD: in validateInstruction()
7936 case ARM::LDMIB_UPD: in validateInstruction()
7937 case ARM::LDMDA_UPD: in validateInstruction()
7946 case ARM::t2LDMIA: in validateInstruction()
7947 case ARM::t2LDMDB: in validateInstruction()
7951 case ARM::t2STMIA: in validateInstruction()
7952 case ARM::t2STMDB: in validateInstruction()
7956 case ARM::t2LDMIA_UPD: in validateInstruction()
7957 case ARM::t2LDMDB_UPD: in validateInstruction()
7958 case ARM::t2STMIA_UPD: in validateInstruction()
7959 case ARM::t2STMDB_UPD: in validateInstruction()
7964 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in validateInstruction()
7973 case ARM::sysLDMIA_UPD: in validateInstruction()
7974 case ARM::sysLDMDA_UPD: in validateInstruction()
7975 case ARM::sysLDMDB_UPD: in validateInstruction()
7976 case ARM::sysLDMIB_UPD: in validateInstruction()
7977 if (!listContainsReg(Inst, 3, ARM::PC)) in validateInstruction()
7982 case ARM::sysSTMIA_UPD: in validateInstruction()
7983 case ARM::sysSTMDA_UPD: in validateInstruction()
7984 case ARM::sysSTMDB_UPD: in validateInstruction()
7985 case ARM::sysSTMIB_UPD: in validateInstruction()
7988 case ARM::tMUL: in validateInstruction()
8009 case ARM::tPOP: { in validateInstruction()
8011 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && in validateInstruction()
8019 case ARM::tPUSH: { in validateInstruction()
8021 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && in validateInstruction()
8029 case ARM::tSTMIA_UPD: { in validateInstruction()
8048 case ARM::tADDrSP: in validateInstruction()
8058 case ARM::t2ADDrr: in validateInstruction()
8059 case ARM::t2ADDrs: in validateInstruction()
8060 case ARM::t2SUBrr: in validateInstruction()
8061 case ARM::t2SUBrs: in validateInstruction()
8062 if (Inst.getOperand(0).getReg() == ARM::SP && in validateInstruction()
8063 Inst.getOperand(1).getReg() != ARM::SP) in validateInstruction()
8069 case ARM::tB: in validateInstruction()
8073 case ARM::t2B: { in validateInstruction()
8083 case ARM::tBcc: in validateInstruction()
8087 case ARM::t2Bcc: { in validateInstruction()
8093 case ARM::tCBZ: in validateInstruction()
8094 case ARM::tCBNZ: { in validateInstruction()
8099 case ARM::MOVi16: in validateInstruction()
8100 case ARM::MOVTi16: in validateInstruction()
8101 case ARM::t2MOVi16: in validateInstruction()
8102 case ARM::t2MOVTi16: in validateInstruction()
8124 case ARM::tADDi8: { in validateInstruction()
8132 case ARM::tMOVi8: { in validateInstruction()
8140 case ARM::HINT: in validateInstruction()
8141 case ARM::t2HINT: { in validateInstruction()
8156 case ARM::t2BFi: in validateInstruction()
8157 case ARM::t2BFr: in validateInstruction()
8158 case ARM::t2BFLi: in validateInstruction()
8159 case ARM::t2BFLr: { in validateInstruction()
8165 if (Opcode == ARM::t2BFi) { in validateInstruction()
8169 } else if (Opcode == ARM::t2BFLi) { in validateInstruction()
8176 case ARM::t2BFic: { in validateInstruction()
8199 case ARM::t2CLRM: { in validateInstruction()
8202 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains( in validateInstruction()
8211 case ARM::DSB: in validateInstruction()
8212 case ARM::t2DSB: { in validateInstruction()
8231 case ARM::VMOVRRS: { in validateInstruction()
8240 case ARM::VMOVSRR: { in validateInstruction()
8249 case ARM::VLDMDIA: in validateInstruction()
8250 case ARM::VSTMDIA: { in validateInstruction()
8258 case ARM::MVE_VQDMULLs32bh: in validateInstruction()
8259 case ARM::MVE_VQDMULLs32th: in validateInstruction()
8260 case ARM::MVE_VCMULf32: in validateInstruction()
8261 case ARM::MVE_VMULLBs32: in validateInstruction()
8262 case ARM::MVE_VMULLTs32: in validateInstruction()
8263 case ARM::MVE_VMULLBu32: in validateInstruction()
8264 case ARM::MVE_VMULLTu32: { in validateInstruction()
8275 case ARM::MVE_VREV64_8: in validateInstruction()
8276 case ARM::MVE_VREV64_16: in validateInstruction()
8277 case ARM::MVE_VREV64_32: in validateInstruction()
8278 case ARM::MVE_VQDMULL_qr_s32bh: in validateInstruction()
8279 case ARM::MVE_VQDMULL_qr_s32th: { in validateInstruction()
8286 case ARM::MVE_VCADDi32: in validateInstruction()
8287 case ARM::MVE_VCADDf32: in validateInstruction()
8288 case ARM::MVE_VHCADDs32: { in validateInstruction()
8295 case ARM::MVE_VMOV_rr_q: { in validateInstruction()
8303 case ARM::MVE_VMOV_q_rr: { in validateInstruction()
8311 case ARM::MVE_SQRSHR: in validateInstruction()
8312 case ARM::MVE_UQRSHL: { in validateInstruction()
8319 case ARM::UMAAL: in validateInstruction()
8320 case ARM::UMLAL: in validateInstruction()
8321 case ARM::UMULL: in validateInstruction()
8322 case ARM::t2UMAAL: in validateInstruction()
8323 case ARM::t2UMLAL: in validateInstruction()
8324 case ARM::t2UMULL: in validateInstruction()
8325 case ARM::SMLAL: in validateInstruction()
8326 case ARM::SMLALBB: in validateInstruction()
8327 case ARM::SMLALBT: in validateInstruction()
8328 case ARM::SMLALD: in validateInstruction()
8329 case ARM::SMLALDX: in validateInstruction()
8330 case ARM::SMLALTB: in validateInstruction()
8331 case ARM::SMLALTT: in validateInstruction()
8332 case ARM::SMLSLD: in validateInstruction()
8333 case ARM::SMLSLDX: in validateInstruction()
8334 case ARM::SMULL: in validateInstruction()
8335 case ARM::t2SMLAL: in validateInstruction()
8336 case ARM::t2SMLALBB: in validateInstruction()
8337 case ARM::t2SMLALBT: in validateInstruction()
8338 case ARM::t2SMLALD: in validateInstruction()
8339 case ARM::t2SMLALDX: in validateInstruction()
8340 case ARM::t2SMLALTB: in validateInstruction()
8341 case ARM::t2SMLALTT: in validateInstruction()
8342 case ARM::t2SMLSLD: in validateInstruction()
8343 case ARM::t2SMLSLDX: in validateInstruction()
8344 case ARM::t2SMULL: { in validateInstruction()
8354 case ARM::CDE_CX1: in validateInstruction()
8355 case ARM::CDE_CX1A: in validateInstruction()
8356 case ARM::CDE_CX1D: in validateInstruction()
8357 case ARM::CDE_CX1DA: in validateInstruction()
8358 case ARM::CDE_CX2: in validateInstruction()
8359 case ARM::CDE_CX2A: in validateInstruction()
8360 case ARM::CDE_CX2D: in validateInstruction()
8361 case ARM::CDE_CX2DA: in validateInstruction()
8362 case ARM::CDE_CX3: in validateInstruction()
8363 case ARM::CDE_CX3A: in validateInstruction()
8364 case ARM::CDE_CX3D: in validateInstruction()
8365 case ARM::CDE_CX3DA: in validateInstruction()
8366 case ARM::CDE_VCX1_vec: in validateInstruction()
8367 case ARM::CDE_VCX1_fpsp: in validateInstruction()
8368 case ARM::CDE_VCX1_fpdp: in validateInstruction()
8369 case ARM::CDE_VCX1A_vec: in validateInstruction()
8370 case ARM::CDE_VCX1A_fpsp: in validateInstruction()
8371 case ARM::CDE_VCX1A_fpdp: in validateInstruction()
8372 case ARM::CDE_VCX2_vec: in validateInstruction()
8373 case ARM::CDE_VCX2_fpsp: in validateInstruction()
8374 case ARM::CDE_VCX2_fpdp: in validateInstruction()
8375 case ARM::CDE_VCX2A_vec: in validateInstruction()
8376 case ARM::CDE_VCX2A_fpsp: in validateInstruction()
8377 case ARM::CDE_VCX2A_fpdp: in validateInstruction()
8378 case ARM::CDE_VCX3_vec: in validateInstruction()
8379 case ARM::CDE_VCX3_fpsp: in validateInstruction()
8380 case ARM::CDE_VCX3_fpdp: in validateInstruction()
8381 case ARM::CDE_VCX3A_vec: in validateInstruction()
8382 case ARM::CDE_VCX3A_fpsp: in validateInstruction()
8383 case ARM::CDE_VCX3A_fpdp: { in validateInstruction()
8387 if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI)) in validateInstruction()
8396 case ARM::t2CDP: in validateInstruction()
8397 case ARM::t2CDP2: in validateInstruction()
8398 case ARM::t2LDC2L_OFFSET: in validateInstruction()
8399 case ARM::t2LDC2L_OPTION: in validateInstruction()
8400 case ARM::t2LDC2L_POST: in validateInstruction()
8401 case ARM::t2LDC2L_PRE: in validateInstruction()
8402 case ARM::t2LDC2_OFFSET: in validateInstruction()
8403 case ARM::t2LDC2_OPTION: in validateInstruction()
8404 case ARM::t2LDC2_POST: in validateInstruction()
8405 case ARM::t2LDC2_PRE: in validateInstruction()
8406 case ARM::t2LDCL_OFFSET: in validateInstruction()
8407 case ARM::t2LDCL_OPTION: in validateInstruction()
8408 case ARM::t2LDCL_POST: in validateInstruction()
8409 case ARM::t2LDCL_PRE: in validateInstruction()
8410 case ARM::t2LDC_OFFSET: in validateInstruction()
8411 case ARM::t2LDC_OPTION: in validateInstruction()
8412 case ARM::t2LDC_POST: in validateInstruction()
8413 case ARM::t2LDC_PRE: in validateInstruction()
8414 case ARM::t2MCR: in validateInstruction()
8415 case ARM::t2MCR2: in validateInstruction()
8416 case ARM::t2MCRR: in validateInstruction()
8417 case ARM::t2MCRR2: in validateInstruction()
8418 case ARM::t2MRC: in validateInstruction()
8419 case ARM::t2MRC2: in validateInstruction()
8420 case ARM::t2MRRC: in validateInstruction()
8421 case ARM::t2MRRC2: in validateInstruction()
8422 case ARM::t2STC2L_OFFSET: in validateInstruction()
8423 case ARM::t2STC2L_OPTION: in validateInstruction()
8424 case ARM::t2STC2L_POST: in validateInstruction()
8425 case ARM::t2STC2L_PRE: in validateInstruction()
8426 case ARM::t2STC2_OFFSET: in validateInstruction()
8427 case ARM::t2STC2_OPTION: in validateInstruction()
8428 case ARM::t2STC2_POST: in validateInstruction()
8429 case ARM::t2STC2_PRE: in validateInstruction()
8430 case ARM::t2STCL_OFFSET: in validateInstruction()
8431 case ARM::t2STCL_OPTION: in validateInstruction()
8432 case ARM::t2STCL_POST: in validateInstruction()
8433 case ARM::t2STCL_PRE: in validateInstruction()
8434 case ARM::t2STC_OFFSET: in validateInstruction()
8435 case ARM::t2STC_OPTION: in validateInstruction()
8436 case ARM::t2STC_POST: in validateInstruction()
8437 case ARM::t2STC_PRE: { in validateInstruction()
8442 if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2) in validateInstruction()
8444 else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2) in validateInstruction()
8450 if (ARM::isCDECoproc(Coproc, *STI)) in validateInstruction()
8464 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
8465 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
8466 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
8467 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
8468 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
8469 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
8470 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; in getRealVSTOpcode()
8471 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; in getRealVSTOpcode()
8472 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; in getRealVSTOpcode()
8475 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
8476 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
8477 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
8478 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
8479 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
8481 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
8482 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
8483 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
8484 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
8485 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
8487 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; in getRealVSTOpcode()
8488 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; in getRealVSTOpcode()
8489 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; in getRealVSTOpcode()
8490 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; in getRealVSTOpcode()
8491 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; in getRealVSTOpcode()
8494 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
8495 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
8496 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
8497 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
8498 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
8499 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
8500 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
8501 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
8502 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
8503 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
8504 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; in getRealVSTOpcode()
8505 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; in getRealVSTOpcode()
8506 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; in getRealVSTOpcode()
8507 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; in getRealVSTOpcode()
8508 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; in getRealVSTOpcode()
8511 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
8512 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
8513 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
8514 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
8515 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
8516 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
8517 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
8518 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
8519 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
8520 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
8521 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
8522 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
8523 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; in getRealVSTOpcode()
8524 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; in getRealVSTOpcode()
8525 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; in getRealVSTOpcode()
8526 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; in getRealVSTOpcode()
8527 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; in getRealVSTOpcode()
8528 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; in getRealVSTOpcode()
8531 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
8532 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
8533 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
8534 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
8535 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
8536 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
8537 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
8538 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
8539 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
8540 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
8541 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; in getRealVSTOpcode()
8542 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; in getRealVSTOpcode()
8543 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; in getRealVSTOpcode()
8544 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; in getRealVSTOpcode()
8545 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; in getRealVSTOpcode()
8548 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
8549 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
8550 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
8551 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
8552 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
8553 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
8554 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
8555 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
8556 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
8557 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
8558 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
8559 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
8560 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; in getRealVSTOpcode()
8561 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; in getRealVSTOpcode()
8562 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; in getRealVSTOpcode()
8563 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; in getRealVSTOpcode()
8564 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; in getRealVSTOpcode()
8565 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; in getRealVSTOpcode()
8573 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
8574 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
8575 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
8576 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
8577 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
8578 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
8579 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; in getRealVLDOpcode()
8580 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; in getRealVLDOpcode()
8581 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; in getRealVLDOpcode()
8584 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
8585 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
8586 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
8587 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
8588 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
8589 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
8590 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
8591 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
8592 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
8593 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
8594 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; in getRealVLDOpcode()
8595 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; in getRealVLDOpcode()
8596 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; in getRealVLDOpcode()
8597 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; in getRealVLDOpcode()
8598 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; in getRealVLDOpcode()
8601 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
8602 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
8603 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
8604 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
8605 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
8606 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
8607 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
8608 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
8609 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
8610 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
8611 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
8612 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
8613 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; in getRealVLDOpcode()
8614 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; in getRealVLDOpcode()
8615 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; in getRealVLDOpcode()
8616 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; in getRealVLDOpcode()
8617 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; in getRealVLDOpcode()
8618 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; in getRealVLDOpcode()
8621 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
8622 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
8623 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
8624 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
8625 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
8626 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
8627 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
8628 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
8629 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
8630 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
8631 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; in getRealVLDOpcode()
8632 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; in getRealVLDOpcode()
8633 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; in getRealVLDOpcode()
8634 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; in getRealVLDOpcode()
8635 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; in getRealVLDOpcode()
8638 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
8639 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
8640 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
8641 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
8642 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
8643 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
8644 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
8645 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
8646 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
8647 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
8648 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
8649 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
8650 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; in getRealVLDOpcode()
8651 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; in getRealVLDOpcode()
8652 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; in getRealVLDOpcode()
8653 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; in getRealVLDOpcode()
8654 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; in getRealVLDOpcode()
8655 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; in getRealVLDOpcode()
8658 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
8659 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
8660 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
8661 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
8662 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
8663 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
8664 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
8665 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
8666 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
8667 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
8668 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; in getRealVLDOpcode()
8669 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; in getRealVLDOpcode()
8670 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; in getRealVLDOpcode()
8671 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; in getRealVLDOpcode()
8672 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; in getRealVLDOpcode()
8675 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
8676 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
8677 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
8678 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
8679 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
8680 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
8681 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
8682 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
8683 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
8684 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
8685 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
8686 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
8687 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; in getRealVLDOpcode()
8688 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; in getRealVLDOpcode()
8689 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; in getRealVLDOpcode()
8690 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; in getRealVLDOpcode()
8691 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; in getRealVLDOpcode()
8692 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; in getRealVLDOpcode()
8695 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
8696 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
8697 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
8698 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
8699 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
8700 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
8701 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
8702 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
8703 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
8704 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
8705 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
8706 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
8707 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; in getRealVLDOpcode()
8708 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; in getRealVLDOpcode()
8709 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; in getRealVLDOpcode()
8710 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; in getRealVLDOpcode()
8711 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; in getRealVLDOpcode()
8712 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; in getRealVLDOpcode()
8732 case ARM::LDRT_POST: in processInstruction()
8733 case ARM::LDRBT_POST: { in processInstruction()
8735 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM in processInstruction()
8736 : ARM::LDRBT_POST_IMM; in processInstruction()
8750 case ARM::LDRSBTii: in processInstruction()
8751 case ARM::LDRHTii: in processInstruction()
8752 case ARM::LDRSHTii: { in processInstruction()
8755 if (Inst.getOpcode() == ARM::LDRSBTii) in processInstruction()
8756 TmpInst.setOpcode(ARM::LDRSBTi); in processInstruction()
8757 else if (Inst.getOpcode() == ARM::LDRHTii) in processInstruction()
8758 TmpInst.setOpcode(ARM::LDRHTi); in processInstruction()
8759 else if (Inst.getOpcode() == ARM::LDRSHTii) in processInstruction()
8760 TmpInst.setOpcode(ARM::LDRSHTi); in processInstruction()
8770 case ARM::STRT_POST: in processInstruction()
8771 case ARM::STRBT_POST: { in processInstruction()
8773 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM in processInstruction()
8774 : ARM::STRBT_POST_IMM; in processInstruction()
8788 case ARM::ADDri: { in processInstruction()
8789 if (Inst.getOperand(1).getReg() != ARM::PC || in processInstruction()
8794 TmpInst.setOpcode(ARM::ADR); in processInstruction()
8825 case ARM::t2LDR_PRE_imm: in processInstruction()
8826 case ARM::t2LDR_POST_imm: { in processInstruction()
8828 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE in processInstruction()
8829 : ARM::t2LDR_POST); in processInstruction()
8839 case ARM::t2STR_PRE_imm: in processInstruction()
8840 case ARM::t2STR_POST_imm: { in processInstruction()
8842 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE in processInstruction()
8843 : ARM::t2STR_POST); in processInstruction()
8853 case ARM::t2LDRB_OFFSET_imm: { in processInstruction()
8855 TmpInst.setOpcode(ARM::t2LDRBi8); in processInstruction()
8863 case ARM::t2LDRB_PRE_imm: in processInstruction()
8864 case ARM::t2LDRB_POST_imm: { in processInstruction()
8866 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRB_PRE_imm in processInstruction()
8867 ? ARM::t2LDRB_PRE in processInstruction()
8868 : ARM::t2LDRB_POST); in processInstruction()
8878 case ARM::t2STRB_OFFSET_imm: { in processInstruction()
8880 TmpInst.setOpcode(ARM::t2STRBi8); in processInstruction()
8888 case ARM::t2STRB_PRE_imm: in processInstruction()
8889 case ARM::t2STRB_POST_imm: { in processInstruction()
8891 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRB_PRE_imm in processInstruction()
8892 ? ARM::t2STRB_PRE in processInstruction()
8893 : ARM::t2STRB_POST); in processInstruction()
8903 case ARM::t2LDRH_OFFSET_imm: { in processInstruction()
8905 TmpInst.setOpcode(ARM::t2LDRHi8); in processInstruction()
8913 case ARM::t2LDRH_PRE_imm: in processInstruction()
8914 case ARM::t2LDRH_POST_imm: { in processInstruction()
8916 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRH_PRE_imm in processInstruction()
8917 ? ARM::t2LDRH_PRE in processInstruction()
8918 : ARM::t2LDRH_POST); in processInstruction()
8928 case ARM::t2STRH_OFFSET_imm: { in processInstruction()
8930 TmpInst.setOpcode(ARM::t2STRHi8); in processInstruction()
8938 case ARM::t2STRH_PRE_imm: in processInstruction()
8939 case ARM::t2STRH_POST_imm: { in processInstruction()
8941 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRH_PRE_imm in processInstruction()
8942 ? ARM::t2STRH_PRE in processInstruction()
8943 : ARM::t2STRH_POST); in processInstruction()
8953 case ARM::t2LDRSB_OFFSET_imm: { in processInstruction()
8955 TmpInst.setOpcode(ARM::t2LDRSBi8); in processInstruction()
8963 case ARM::t2LDRSB_PRE_imm: in processInstruction()
8964 case ARM::t2LDRSB_POST_imm: { in processInstruction()
8966 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRSB_PRE_imm in processInstruction()
8967 ? ARM::t2LDRSB_PRE in processInstruction()
8968 : ARM::t2LDRSB_POST); in processInstruction()
8978 case ARM::t2LDRSH_OFFSET_imm: { in processInstruction()
8980 TmpInst.setOpcode(ARM::t2LDRSHi8); in processInstruction()
8988 case ARM::t2LDRSH_PRE_imm: in processInstruction()
8989 case ARM::t2LDRSH_POST_imm: { in processInstruction()
8991 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRSH_PRE_imm in processInstruction()
8992 ? ARM::t2LDRSH_PRE in processInstruction()
8993 : ARM::t2LDRSH_POST); in processInstruction()
9003 case ARM::t2LDRpcrel: in processInstruction()
9008 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
9010 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
9012 case ARM::t2LDRBpcrel: in processInstruction()
9013 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
9015 case ARM::t2LDRHpcrel: in processInstruction()
9016 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
9018 case ARM::t2LDRSBpcrel: in processInstruction()
9019 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
9021 case ARM::t2LDRSHpcrel: in processInstruction()
9022 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
9024 case ARM::LDRConstPool: in processInstruction()
9025 case ARM::tLDRConstPool: in processInstruction()
9026 case ARM::t2LDRConstPool: { in processInstruction()
9031 if (Inst.getOpcode() == ARM::LDRConstPool) in processInstruction()
9032 TmpInst.setOpcode(ARM::LDRi12); in processInstruction()
9033 else if (Inst.getOpcode() == ARM::tLDRConstPool) in processInstruction()
9034 TmpInst.setOpcode(ARM::tLDRpci); in processInstruction()
9035 else if (Inst.getOpcode() == ARM::t2LDRConstPool) in processInstruction()
9036 TmpInst.setOpcode(ARM::t2LDRpci); in processInstruction()
9044 Inst.getOperand(0).getReg() != ARM::PC && in processInstruction()
9045 Inst.getOperand(0).getReg() != ARM::SP) { in processInstruction()
9050 if (Inst.getOpcode() == ARM::LDRConstPool) { in processInstruction()
9054 TmpInst.setOpcode(ARM::MOVi); in processInstruction()
9058 TmpInst.setOpcode(ARM::MVNi); in processInstruction()
9062 TmpInst.setOpcode(ARM::MOVi16); in processInstruction()
9072 TmpInst.setOpcode(ARM::t2MOVi); in processInstruction()
9075 TmpInst.setOpcode(ARM::t2MVNi); in processInstruction()
9080 TmpInst.setOpcode(ARM::t2MOVi16); in processInstruction()
9103 if (TmpInst.getOpcode() == ARM::LDRi12) in processInstruction()
9111 case ARM::VST1LNdWB_register_Asm_8: in processInstruction()
9112 case ARM::VST1LNdWB_register_Asm_16: in processInstruction()
9113 case ARM::VST1LNdWB_register_Asm_32: { in processInstruction()
9131 case ARM::VST2LNdWB_register_Asm_8: in processInstruction()
9132 case ARM::VST2LNdWB_register_Asm_16: in processInstruction()
9133 case ARM::VST2LNdWB_register_Asm_32: in processInstruction()
9134 case ARM::VST2LNqWB_register_Asm_16: in processInstruction()
9135 case ARM::VST2LNqWB_register_Asm_32: { in processInstruction()
9155 case ARM::VST3LNdWB_register_Asm_8: in processInstruction()
9156 case ARM::VST3LNdWB_register_Asm_16: in processInstruction()
9157 case ARM::VST3LNdWB_register_Asm_32: in processInstruction()
9158 case ARM::VST3LNqWB_register_Asm_16: in processInstruction()
9159 case ARM::VST3LNqWB_register_Asm_32: { in processInstruction()
9181 case ARM::VST4LNdWB_register_Asm_8: in processInstruction()
9182 case ARM::VST4LNdWB_register_Asm_16: in processInstruction()
9183 case ARM::VST4LNdWB_register_Asm_32: in processInstruction()
9184 case ARM::VST4LNqWB_register_Asm_16: in processInstruction()
9185 case ARM::VST4LNqWB_register_Asm_32: { in processInstruction()
9209 case ARM::VST1LNdWB_fixed_Asm_8: in processInstruction()
9210 case ARM::VST1LNdWB_fixed_Asm_16: in processInstruction()
9211 case ARM::VST1LNdWB_fixed_Asm_32: { in processInstruction()
9229 case ARM::VST2LNdWB_fixed_Asm_8: in processInstruction()
9230 case ARM::VST2LNdWB_fixed_Asm_16: in processInstruction()
9231 case ARM::VST2LNdWB_fixed_Asm_32: in processInstruction()
9232 case ARM::VST2LNqWB_fixed_Asm_16: in processInstruction()
9233 case ARM::VST2LNqWB_fixed_Asm_32: { in processInstruction()
9253 case ARM::VST3LNdWB_fixed_Asm_8: in processInstruction()
9254 case ARM::VST3LNdWB_fixed_Asm_16: in processInstruction()
9255 case ARM::VST3LNdWB_fixed_Asm_32: in processInstruction()
9256 case ARM::VST3LNqWB_fixed_Asm_16: in processInstruction()
9257 case ARM::VST3LNqWB_fixed_Asm_32: { in processInstruction()
9279 case ARM::VST4LNdWB_fixed_Asm_8: in processInstruction()
9280 case ARM::VST4LNdWB_fixed_Asm_16: in processInstruction()
9281 case ARM::VST4LNdWB_fixed_Asm_32: in processInstruction()
9282 case ARM::VST4LNqWB_fixed_Asm_16: in processInstruction()
9283 case ARM::VST4LNqWB_fixed_Asm_32: { in processInstruction()
9307 case ARM::VST1LNdAsm_8: in processInstruction()
9308 case ARM::VST1LNdAsm_16: in processInstruction()
9309 case ARM::VST1LNdAsm_32: { in processInstruction()
9325 case ARM::VST2LNdAsm_8: in processInstruction()
9326 case ARM::VST2LNdAsm_16: in processInstruction()
9327 case ARM::VST2LNdAsm_32: in processInstruction()
9328 case ARM::VST2LNqAsm_16: in processInstruction()
9329 case ARM::VST2LNqAsm_32: { in processInstruction()
9347 case ARM::VST3LNdAsm_8: in processInstruction()
9348 case ARM::VST3LNdAsm_16: in processInstruction()
9349 case ARM::VST3LNdAsm_32: in processInstruction()
9350 case ARM::VST3LNqAsm_16: in processInstruction()
9351 case ARM::VST3LNqAsm_32: { in processInstruction()
9371 case ARM::VST4LNdAsm_8: in processInstruction()
9372 case ARM::VST4LNdAsm_16: in processInstruction()
9373 case ARM::VST4LNdAsm_32: in processInstruction()
9374 case ARM::VST4LNqAsm_16: in processInstruction()
9375 case ARM::VST4LNqAsm_32: { in processInstruction()
9398 case ARM::VLD1LNdWB_register_Asm_8: in processInstruction()
9399 case ARM::VLD1LNdWB_register_Asm_16: in processInstruction()
9400 case ARM::VLD1LNdWB_register_Asm_32: { in processInstruction()
9419 case ARM::VLD2LNdWB_register_Asm_8: in processInstruction()
9420 case ARM::VLD2LNdWB_register_Asm_16: in processInstruction()
9421 case ARM::VLD2LNdWB_register_Asm_32: in processInstruction()
9422 case ARM::VLD2LNqWB_register_Asm_16: in processInstruction()
9423 case ARM::VLD2LNqWB_register_Asm_32: { in processInstruction()
9446 case ARM::VLD3LNdWB_register_Asm_8: in processInstruction()
9447 case ARM::VLD3LNdWB_register_Asm_16: in processInstruction()
9448 case ARM::VLD3LNdWB_register_Asm_32: in processInstruction()
9449 case ARM::VLD3LNqWB_register_Asm_16: in processInstruction()
9450 case ARM::VLD3LNqWB_register_Asm_32: { in processInstruction()
9477 case ARM::VLD4LNdWB_register_Asm_8: in processInstruction()
9478 case ARM::VLD4LNdWB_register_Asm_16: in processInstruction()
9479 case ARM::VLD4LNdWB_register_Asm_32: in processInstruction()
9480 case ARM::VLD4LNqWB_register_Asm_16: in processInstruction()
9481 case ARM::VLD4LNqWB_register_Asm_32: { in processInstruction()
9512 case ARM::VLD1LNdWB_fixed_Asm_8: in processInstruction()
9513 case ARM::VLD1LNdWB_fixed_Asm_16: in processInstruction()
9514 case ARM::VLD1LNdWB_fixed_Asm_32: { in processInstruction()
9533 case ARM::VLD2LNdWB_fixed_Asm_8: in processInstruction()
9534 case ARM::VLD2LNdWB_fixed_Asm_16: in processInstruction()
9535 case ARM::VLD2LNdWB_fixed_Asm_32: in processInstruction()
9536 case ARM::VLD2LNqWB_fixed_Asm_16: in processInstruction()
9537 case ARM::VLD2LNqWB_fixed_Asm_32: { in processInstruction()
9560 case ARM::VLD3LNdWB_fixed_Asm_8: in processInstruction()
9561 case ARM::VLD3LNdWB_fixed_Asm_16: in processInstruction()
9562 case ARM::VLD3LNdWB_fixed_Asm_32: in processInstruction()
9563 case ARM::VLD3LNqWB_fixed_Asm_16: in processInstruction()
9564 case ARM::VLD3LNqWB_fixed_Asm_32: { in processInstruction()
9591 case ARM::VLD4LNdWB_fixed_Asm_8: in processInstruction()
9592 case ARM::VLD4LNdWB_fixed_Asm_16: in processInstruction()
9593 case ARM::VLD4LNdWB_fixed_Asm_32: in processInstruction()
9594 case ARM::VLD4LNqWB_fixed_Asm_16: in processInstruction()
9595 case ARM::VLD4LNqWB_fixed_Asm_32: { in processInstruction()
9626 case ARM::VLD1LNdAsm_8: in processInstruction()
9627 case ARM::VLD1LNdAsm_16: in processInstruction()
9628 case ARM::VLD1LNdAsm_32: { in processInstruction()
9645 case ARM::VLD2LNdAsm_8: in processInstruction()
9646 case ARM::VLD2LNdAsm_16: in processInstruction()
9647 case ARM::VLD2LNdAsm_32: in processInstruction()
9648 case ARM::VLD2LNqAsm_16: in processInstruction()
9649 case ARM::VLD2LNqAsm_32: { in processInstruction()
9670 case ARM::VLD3LNdAsm_8: in processInstruction()
9671 case ARM::VLD3LNdAsm_16: in processInstruction()
9672 case ARM::VLD3LNdAsm_32: in processInstruction()
9673 case ARM::VLD3LNqAsm_16: in processInstruction()
9674 case ARM::VLD3LNqAsm_32: { in processInstruction()
9699 case ARM::VLD4LNdAsm_8: in processInstruction()
9700 case ARM::VLD4LNdAsm_16: in processInstruction()
9701 case ARM::VLD4LNdAsm_32: in processInstruction()
9702 case ARM::VLD4LNqAsm_16: in processInstruction()
9703 case ARM::VLD4LNqAsm_32: { in processInstruction()
9733 case ARM::VLD3DUPdAsm_8: in processInstruction()
9734 case ARM::VLD3DUPdAsm_16: in processInstruction()
9735 case ARM::VLD3DUPdAsm_32: in processInstruction()
9736 case ARM::VLD3DUPqAsm_8: in processInstruction()
9737 case ARM::VLD3DUPqAsm_16: in processInstruction()
9738 case ARM::VLD3DUPqAsm_32: { in processInstruction()
9755 case ARM::VLD3DUPdWB_fixed_Asm_8: in processInstruction()
9756 case ARM::VLD3DUPdWB_fixed_Asm_16: in processInstruction()
9757 case ARM::VLD3DUPdWB_fixed_Asm_32: in processInstruction()
9758 case ARM::VLD3DUPqWB_fixed_Asm_8: in processInstruction()
9759 case ARM::VLD3DUPqWB_fixed_Asm_16: in processInstruction()
9760 case ARM::VLD3DUPqWB_fixed_Asm_32: { in processInstruction()
9779 case ARM::VLD3DUPdWB_register_Asm_8: in processInstruction()
9780 case ARM::VLD3DUPdWB_register_Asm_16: in processInstruction()
9781 case ARM::VLD3DUPdWB_register_Asm_32: in processInstruction()
9782 case ARM::VLD3DUPqWB_register_Asm_8: in processInstruction()
9783 case ARM::VLD3DUPqWB_register_Asm_16: in processInstruction()
9784 case ARM::VLD3DUPqWB_register_Asm_32: { in processInstruction()
9804 case ARM::VLD3dAsm_8: in processInstruction()
9805 case ARM::VLD3dAsm_16: in processInstruction()
9806 case ARM::VLD3dAsm_32: in processInstruction()
9807 case ARM::VLD3qAsm_8: in processInstruction()
9808 case ARM::VLD3qAsm_16: in processInstruction()
9809 case ARM::VLD3qAsm_32: { in processInstruction()
9826 case ARM::VLD3dWB_fixed_Asm_8: in processInstruction()
9827 case ARM::VLD3dWB_fixed_Asm_16: in processInstruction()
9828 case ARM::VLD3dWB_fixed_Asm_32: in processInstruction()
9829 case ARM::VLD3qWB_fixed_Asm_8: in processInstruction()
9830 case ARM::VLD3qWB_fixed_Asm_16: in processInstruction()
9831 case ARM::VLD3qWB_fixed_Asm_32: { in processInstruction()
9850 case ARM::VLD3dWB_register_Asm_8: in processInstruction()
9851 case ARM::VLD3dWB_register_Asm_16: in processInstruction()
9852 case ARM::VLD3dWB_register_Asm_32: in processInstruction()
9853 case ARM::VLD3qWB_register_Asm_8: in processInstruction()
9854 case ARM::VLD3qWB_register_Asm_16: in processInstruction()
9855 case ARM::VLD3qWB_register_Asm_32: { in processInstruction()
9875 case ARM::VLD4DUPdAsm_8: in processInstruction()
9876 case ARM::VLD4DUPdAsm_16: in processInstruction()
9877 case ARM::VLD4DUPdAsm_32: in processInstruction()
9878 case ARM::VLD4DUPqAsm_8: in processInstruction()
9879 case ARM::VLD4DUPqAsm_16: in processInstruction()
9880 case ARM::VLD4DUPqAsm_32: { in processInstruction()
9899 case ARM::VLD4DUPdWB_fixed_Asm_8: in processInstruction()
9900 case ARM::VLD4DUPdWB_fixed_Asm_16: in processInstruction()
9901 case ARM::VLD4DUPdWB_fixed_Asm_32: in processInstruction()
9902 case ARM::VLD4DUPqWB_fixed_Asm_8: in processInstruction()
9903 case ARM::VLD4DUPqWB_fixed_Asm_16: in processInstruction()
9904 case ARM::VLD4DUPqWB_fixed_Asm_32: { in processInstruction()
9925 case ARM::VLD4DUPdWB_register_Asm_8: in processInstruction()
9926 case ARM::VLD4DUPdWB_register_Asm_16: in processInstruction()
9927 case ARM::VLD4DUPdWB_register_Asm_32: in processInstruction()
9928 case ARM::VLD4DUPqWB_register_Asm_8: in processInstruction()
9929 case ARM::VLD4DUPqWB_register_Asm_16: in processInstruction()
9930 case ARM::VLD4DUPqWB_register_Asm_32: { in processInstruction()
9952 case ARM::VLD4dAsm_8: in processInstruction()
9953 case ARM::VLD4dAsm_16: in processInstruction()
9954 case ARM::VLD4dAsm_32: in processInstruction()
9955 case ARM::VLD4qAsm_8: in processInstruction()
9956 case ARM::VLD4qAsm_16: in processInstruction()
9957 case ARM::VLD4qAsm_32: { in processInstruction()
9976 case ARM::VLD4dWB_fixed_Asm_8: in processInstruction()
9977 case ARM::VLD4dWB_fixed_Asm_16: in processInstruction()
9978 case ARM::VLD4dWB_fixed_Asm_32: in processInstruction()
9979 case ARM::VLD4qWB_fixed_Asm_8: in processInstruction()
9980 case ARM::VLD4qWB_fixed_Asm_16: in processInstruction()
9981 case ARM::VLD4qWB_fixed_Asm_32: { in processInstruction()
10002 case ARM::VLD4dWB_register_Asm_8: in processInstruction()
10003 case ARM::VLD4dWB_register_Asm_16: in processInstruction()
10004 case ARM::VLD4dWB_register_Asm_32: in processInstruction()
10005 case ARM::VLD4qWB_register_Asm_8: in processInstruction()
10006 case ARM::VLD4qWB_register_Asm_16: in processInstruction()
10007 case ARM::VLD4qWB_register_Asm_32: { in processInstruction()
10029 case ARM::VST3dAsm_8: in processInstruction()
10030 case ARM::VST3dAsm_16: in processInstruction()
10031 case ARM::VST3dAsm_32: in processInstruction()
10032 case ARM::VST3qAsm_8: in processInstruction()
10033 case ARM::VST3qAsm_16: in processInstruction()
10034 case ARM::VST3qAsm_32: { in processInstruction()
10051 case ARM::VST3dWB_fixed_Asm_8: in processInstruction()
10052 case ARM::VST3dWB_fixed_Asm_16: in processInstruction()
10053 case ARM::VST3dWB_fixed_Asm_32: in processInstruction()
10054 case ARM::VST3qWB_fixed_Asm_8: in processInstruction()
10055 case ARM::VST3qWB_fixed_Asm_16: in processInstruction()
10056 case ARM::VST3qWB_fixed_Asm_32: { in processInstruction()
10075 case ARM::VST3dWB_register_Asm_8: in processInstruction()
10076 case ARM::VST3dWB_register_Asm_16: in processInstruction()
10077 case ARM::VST3dWB_register_Asm_32: in processInstruction()
10078 case ARM::VST3qWB_register_Asm_8: in processInstruction()
10079 case ARM::VST3qWB_register_Asm_16: in processInstruction()
10080 case ARM::VST3qWB_register_Asm_32: { in processInstruction()
10100 case ARM::VST4dAsm_8: in processInstruction()
10101 case ARM::VST4dAsm_16: in processInstruction()
10102 case ARM::VST4dAsm_32: in processInstruction()
10103 case ARM::VST4qAsm_8: in processInstruction()
10104 case ARM::VST4qAsm_16: in processInstruction()
10105 case ARM::VST4qAsm_32: { in processInstruction()
10124 case ARM::VST4dWB_fixed_Asm_8: in processInstruction()
10125 case ARM::VST4dWB_fixed_Asm_16: in processInstruction()
10126 case ARM::VST4dWB_fixed_Asm_32: in processInstruction()
10127 case ARM::VST4qWB_fixed_Asm_8: in processInstruction()
10128 case ARM::VST4qWB_fixed_Asm_16: in processInstruction()
10129 case ARM::VST4qWB_fixed_Asm_32: { in processInstruction()
10150 case ARM::VST4dWB_register_Asm_8: in processInstruction()
10151 case ARM::VST4dWB_register_Asm_16: in processInstruction()
10152 case ARM::VST4dWB_register_Asm_32: in processInstruction()
10153 case ARM::VST4qWB_register_Asm_8: in processInstruction()
10154 case ARM::VST4qWB_register_Asm_16: in processInstruction()
10155 case ARM::VST4qWB_register_Asm_32: { in processInstruction()
10177 case ARM::t2LSLri: in processInstruction()
10178 case ARM::t2LSRri: in processInstruction()
10179 case ARM::t2ASRri: in processInstruction()
10182 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10187 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
10188 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
10189 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
10206 case ARM::t2MOVsr: in processInstruction()
10207 case ARM::t2MOVSsr: { in processInstruction()
10216 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && in processInstruction()
10223 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
10224 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; in processInstruction()
10225 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; in processInstruction()
10226 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
10232 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10239 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10243 case ARM::t2MOVsi: in processInstruction()
10244 case ARM::t2MOVSsi: { in processInstruction()
10251 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && in processInstruction()
10269 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr; in processInstruction()
10273 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
10274 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; in processInstruction()
10275 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; in processInstruction()
10276 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
10277 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
10285 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10287 if (newOpc != ARM::t2RRX && !isMov) in processInstruction()
10293 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10298 case ARM::ASRr: in processInstruction()
10299 case ARM::LSRr: in processInstruction()
10300 case ARM::LSLr: in processInstruction()
10301 case ARM::RORr: { in processInstruction()
10305 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
10306 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; in processInstruction()
10307 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; in processInstruction()
10308 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
10312 TmpInst.setOpcode(ARM::MOVsr); in processInstruction()
10323 case ARM::ASRi: in processInstruction()
10324 case ARM::LSRi: in processInstruction()
10325 case ARM::LSLi: in processInstruction()
10326 case ARM::RORi: { in processInstruction()
10330 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
10331 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; in processInstruction()
10332 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; in processInstruction()
10333 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
10337 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; in processInstruction()
10346 if (Opc == ARM::MOVsi) in processInstruction()
10354 case ARM::RRXi: { in processInstruction()
10357 TmpInst.setOpcode(ARM::MOVsi); in processInstruction()
10367 case ARM::t2LDMIA_UPD: { in processInstruction()
10373 TmpInst.setOpcode(ARM::t2LDR_POST); in processInstruction()
10383 case ARM::t2STMDB_UPD: { in processInstruction()
10389 TmpInst.setOpcode(ARM::t2STR_PRE); in processInstruction()
10399 case ARM::LDMIA_UPD: in processInstruction()
10405 TmpInst.setOpcode(ARM::LDR_POST_IMM); in processInstruction()
10417 case ARM::STMDB_UPD: in processInstruction()
10423 TmpInst.setOpcode(ARM::STR_PRE_IMM); in processInstruction()
10433 case ARM::t2ADDri12: in processInstruction()
10434 case ARM::t2SUBri12: in processInstruction()
10435 case ARM::t2ADDspImm12: in processInstruction()
10436 case ARM::t2SUBspImm12: { in processInstruction()
10444 case ARM::t2ADDri12: in processInstruction()
10445 Inst.setOpcode(ARM::t2ADDri); in processInstruction()
10447 case ARM::t2SUBri12: in processInstruction()
10448 Inst.setOpcode(ARM::t2SUBri); in processInstruction()
10450 case ARM::t2ADDspImm12: in processInstruction()
10451 Inst.setOpcode(ARM::t2ADDspImm); in processInstruction()
10453 case ARM::t2SUBspImm12: in processInstruction()
10454 Inst.setOpcode(ARM::t2SUBspImm); in processInstruction()
10461 case ARM::tADDi8: in processInstruction()
10468 Inst.setOpcode(ARM::tADDi3); in processInstruction()
10472 case ARM::tSUBi8: in processInstruction()
10478 Inst.setOpcode(ARM::tSUBi3); in processInstruction()
10482 case ARM::t2ADDri: in processInstruction()
10483 case ARM::t2SUBri: { in processInstruction()
10492 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
10496 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? in processInstruction()
10497 ARM::tADDi8 : ARM::tSUBi8); in processInstruction()
10507 case ARM::t2ADDspImm: in processInstruction()
10508 case ARM::t2SUBspImm: { in processInstruction()
10516 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi in processInstruction()
10517 : ARM::tSUBspi); in processInstruction()
10518 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg in processInstruction()
10519 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg in processInstruction()
10526 case ARM::t2ADDrr: { in processInstruction()
10544 TmpInst.setOpcode(ARM::tADDhirr); in processInstruction()
10553 case ARM::tADDrSP: in processInstruction()
10557 Inst.setOpcode(ARM::t2ADDrr); in processInstruction()
10562 case ARM::tB: in processInstruction()
10565 Inst.setOpcode(ARM::tBcc); in processInstruction()
10569 case ARM::t2B: in processInstruction()
10572 Inst.setOpcode(ARM::t2Bcc); in processInstruction()
10576 case ARM::t2Bcc: in processInstruction()
10579 Inst.setOpcode(ARM::t2B); in processInstruction()
10583 case ARM::tBcc: in processInstruction()
10586 Inst.setOpcode(ARM::tB); in processInstruction()
10590 case ARM::tLDMIA: { in processInstruction()
10605 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); in processInstruction()
10615 case ARM::tSTMIA_UPD: { in processInstruction()
10624 Inst.setOpcode(ARM::t2STMIA_UPD); in processInstruction()
10629 case ARM::tPOP: { in processInstruction()
10634 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) in processInstruction()
10637 Inst.setOpcode(ARM::t2LDMIA_UPD); in processInstruction()
10639 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10640 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10643 case ARM::tPUSH: { in processInstruction()
10645 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) in processInstruction()
10648 Inst.setOpcode(ARM::t2STMDB_UPD); in processInstruction()
10650 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10651 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10654 case ARM::t2MOVi: in processInstruction()
10660 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10664 TmpInst.setOpcode(ARM::tMOVi8); in processInstruction()
10675 case ARM::t2MOVr: in processInstruction()
10681 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
10685 unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr; in processInstruction()
10689 if (Op == ARM::tMOVr) { in processInstruction()
10698 case ARM::t2SXTH: in processInstruction()
10699 case ARM::t2SXTB: in processInstruction()
10700 case ARM::t2UXTH: in processInstruction()
10701 case ARM::t2UXTB: in processInstruction()
10711 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
10712 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
10713 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
10714 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
10728 case ARM::MOVsi: { in processInstruction()
10736 TmpInst.setOpcode(ARM::MOVr); in processInstruction()
10747 case ARM::ANDrsi: in processInstruction()
10748 case ARM::ORRrsi: in processInstruction()
10749 case ARM::EORrsi: in processInstruction()
10750 case ARM::BICrsi: in processInstruction()
10751 case ARM::SUBrsi: in processInstruction()
10752 case ARM::ADDrsi: { in processInstruction()
10758 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; in processInstruction()
10759 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; in processInstruction()
10760 case ARM::EORrsi: newOpc = ARM::EORrr; break; in processInstruction()
10761 case ARM::BICrsi: newOpc = ARM::BICrr; break; in processInstruction()
10762 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; in processInstruction()
10763 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; in processInstruction()
10782 case ARM::ITasm: in processInstruction()
10783 case ARM::t2IT: { in processInstruction()
10791 case ARM::t2LSLrr: in processInstruction()
10792 case ARM::t2LSRrr: in processInstruction()
10793 case ARM::t2ASRrr: in processInstruction()
10794 case ARM::t2SBCrr: in processInstruction()
10795 case ARM::t2RORrr: in processInstruction()
10796 case ARM::t2BICrr: in processInstruction()
10801 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10806 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; in processInstruction()
10807 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; in processInstruction()
10808 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; in processInstruction()
10809 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; in processInstruction()
10810 case ARM::t2RORrr: NewOpc = ARM::tROR; break; in processInstruction()
10811 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; in processInstruction()
10826 case ARM::t2ANDrr: in processInstruction()
10827 case ARM::t2EORrr: in processInstruction()
10828 case ARM::t2ADCrr: in processInstruction()
10829 case ARM::t2ORRrr: in processInstruction()
10837 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10842 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; in processInstruction()
10843 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; in processInstruction()
10844 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; in processInstruction()
10845 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; in processInstruction()
10864 case ARM::MVE_VPST: in processInstruction()
10865 case ARM::MVE_VPTv16i8: in processInstruction()
10866 case ARM::MVE_VPTv8i16: in processInstruction()
10867 case ARM::MVE_VPTv4i32: in processInstruction()
10868 case ARM::MVE_VPTv16u8: in processInstruction()
10869 case ARM::MVE_VPTv8u16: in processInstruction()
10870 case ARM::MVE_VPTv4u32: in processInstruction()
10871 case ARM::MVE_VPTv16s8: in processInstruction()
10872 case ARM::MVE_VPTv8s16: in processInstruction()
10873 case ARM::MVE_VPTv4s32: in processInstruction()
10874 case ARM::MVE_VPTv4f32: in processInstruction()
10875 case ARM::MVE_VPTv8f16: in processInstruction()
10876 case ARM::MVE_VPTv16i8r: in processInstruction()
10877 case ARM::MVE_VPTv8i16r: in processInstruction()
10878 case ARM::MVE_VPTv4i32r: in processInstruction()
10879 case ARM::MVE_VPTv16u8r: in processInstruction()
10880 case ARM::MVE_VPTv8u16r: in processInstruction()
10881 case ARM::MVE_VPTv4u32r: in processInstruction()
10882 case ARM::MVE_VPTv16s8r: in processInstruction()
10883 case ARM::MVE_VPTv8s16r: in processInstruction()
10884 case ARM::MVE_VPTv4s32r: in processInstruction()
10885 case ARM::MVE_VPTv4f32r: in processInstruction()
10886 case ARM::MVE_VPTv8f16r: { in processInstruction()
10914 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
10918 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
10921 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
10925 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) in checkTargetMatchPredicate()
10930 if (Opc == ARM::tADDhirr && !hasV6MOps() && in checkTargetMatchPredicate()
10935 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()
10944 if (Opc == ARM::t2MOVr && !hasV8Ops()) in checkTargetMatchPredicate()
10947 if (Inst.getOperand(0).getReg() == ARM::SP && in checkTargetMatchPredicate()
10948 Inst.getOperand(1).getReg() == ARM::SP) in checkTargetMatchPredicate()
10951 if (Inst.getOperand(4).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
10952 (Inst.getOperand(0).getReg() == ARM::SP || in checkTargetMatchPredicate()
10953 Inst.getOperand(1).getReg() == ARM::SP)) in checkTargetMatchPredicate()
10958 case ARM::VMRS: in checkTargetMatchPredicate()
10959 case ARM::VMSR: in checkTargetMatchPredicate()
10960 case ARM::VMRS_FPCXTS: in checkTargetMatchPredicate()
10961 case ARM::VMRS_FPCXTNS: in checkTargetMatchPredicate()
10962 case ARM::VMSR_FPCXTS: in checkTargetMatchPredicate()
10963 case ARM::VMSR_FPCXTNS: in checkTargetMatchPredicate()
10964 case ARM::VMRS_FPSCR_NZCVQC: in checkTargetMatchPredicate()
10965 case ARM::VMSR_FPSCR_NZCVQC: in checkTargetMatchPredicate()
10966 case ARM::FMSTAT: in checkTargetMatchPredicate()
10967 case ARM::VMRS_VPR: in checkTargetMatchPredicate()
10968 case ARM::VMRS_P0: in checkTargetMatchPredicate()
10969 case ARM::VMSR_VPR: in checkTargetMatchPredicate()
10970 case ARM::VMSR_P0: in checkTargetMatchPredicate()
10973 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP && in checkTargetMatchPredicate()
10977 case ARM::t2TBB: in checkTargetMatchPredicate()
10978 case ARM::t2TBH: in checkTargetMatchPredicate()
10980 if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP)) in checkTargetMatchPredicate()
10988 if (MCID.operands()[I].RegClass == ARM::rGPRRegClassID) { in checkTargetMatchPredicate()
11004 if ((Reg == ARM::SP) && !hasV8Ops()) in checkTargetMatchPredicate()
11006 else if (Reg == ARM::PC) in checkTargetMatchPredicate()
11028 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || in isITBlockTerminator()
11034 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) in isITBlockTerminator()
11088 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) { in MatchInstruction()
11176 if (Inst.getOpcode() == ARM::ITasm) in MatchAndEmitInstruction()
11529 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveArch()
11531 if (ID == ARM::ArchKind::INVALID) in parseDirectiveArch()
11538 ("+" + ARM::getArchName(ID)).str()); in parseDirectiveArch()
11671 ARM::FPUKind ID = ARM::parseFPU(FPU); in parseDirectiveFPU()
11673 if (!ARM::getFPUFeatures(ID, Features)) in parseDirectiveFPU()
11831 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, in parseDirectiveSetFP()
12058 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) in parseDirectivePersonalityIndex()
12144 if (UC.getFPReg() != ARM::SP) in parseDirectiveMovSP()
12151 if (SPReg == ARM::SP || SPReg == ARM::PC) in parseDirectiveMovSP()
12192 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveObjectArch()
12194 if (ID == ARM::ArchKind::INVALID) in parseDirectiveObjectArch()
12287 if (Reg == -1 || !MRI->getRegClass(ARM::GPRRegClassID).contains(Reg)) in parseDirectiveSEHSaveSP()
12638 {ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC}}, in enableArchExtFeature()
12639 {ARM::AEK_AES, in enableArchExtFeature()
12641 {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12642 {ARM::AEK_SHA2, in enableArchExtFeature()
12644 {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12645 {ARM::AEK_CRYPTO, in enableArchExtFeature()
12647 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12648 {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP), in enableArchExtFeature()
12650 {ARM::HasMVEFloatOps}}, in enableArchExtFeature()
12651 {ARM::AEK_FP, in enableArchExtFeature()
12653 {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12654 {(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), in enableArchExtFeature()
12656 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM}}, in enableArchExtFeature()
12657 {ARM::AEK_MP, in enableArchExtFeature()
12659 {ARM::FeatureMP}}, in enableArchExtFeature()
12660 {ARM::AEK_SIMD, in enableArchExtFeature()
12662 {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12663 {ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone}}, in enableArchExtFeature()
12665 {ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization}}, in enableArchExtFeature()
12666 {ARM::AEK_FP16, in enableArchExtFeature()
12668 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16}}, in enableArchExtFeature()
12669 {ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}}, in enableArchExtFeature()
12670 {ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}}, in enableArchExtFeature()
12671 {ARM::AEK_PACBTI, {Feature_HasV8_1MMainlineBit}, {ARM::FeaturePACBTI}}, in enableArchExtFeature()
12673 {ARM::AEK_OS, {}, {}}, in enableArchExtFeature()
12674 {ARM::AEK_IWMMXT, {}, {}}, in enableArchExtFeature()
12675 {ARM::AEK_IWMMXT2, {}, {}}, in enableArchExtFeature()
12676 {ARM::AEK_MAVERICK, {}, {}}, in enableArchExtFeature()
12677 {ARM::AEK_XSCALE, {}, {}}, in enableArchExtFeature()
12680 uint64_t FeatureKind = ARM::parseArchExt(Name); in enableArchExtFeature()
12681 if (FeatureKind == ARM::AEK_INVALID) in enableArchExtFeature()
12776 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) in validateTargetOperandClass()
12781 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) in validateTargetOperandClass()