Home
last modified time | relevance | path

Searched refs:getInstr (Results 1 – 25 of 79) sorted by relevance

1234

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp216 MachineInstr &MI1 = *SU.getInstr(); in apply()
277 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
343 MachineInstr &L0 = *S0.getInstr(); in apply()
356 MachineInstr &L1 = *S1.getInstr(); in apply()
395 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
396 MachineInstr *DstInst = Dst->getInstr(); in adjustSchedDependency()
490 MachineInstr *SrcI = Src->getInstr(); in restoreLatency()
511 MachineInstr *DstI = Dst->getInstr(); in restoreLatency()
557 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
569 MachineInstr &SrcInst = *Src->getInstr(); in isBestZeroLatency()
[all …]
H A DHexagonMachineScheduler.cpp74 if (QII.mayBeCurLoad(*SUd->getInstr())) in hasDependence()
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
157 switch (SU->getInstr()->getOpcode()) { in reserveResources()
159 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
181 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
407 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
[all …]
H A DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
109 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp424 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
518 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
519 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
520 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
675 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
1319 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
1320 MachineInstr &I = *SUI->getInstr(); in isLegalToPacketizeTogether()
1321 MachineInstr &J = *SUJ->getInstr(); in isLegalToPacketizeTogether()
1630 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPruneDependencies()
1631 MachineInstr &I = *SUI->getInstr(); in isLegalToPruneDependencies()
[all …]
H A DHexagonISelLoweringHVX.cpp675 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in createHvxPrefixPred()
1014 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, in extractHvxSubvectorPred()
1139 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in insertHvxSubvectorPred()
1210 SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy, in compressHvxPred()
1499 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMulh()
1532 SDValue T1 = getInstr(Hexagon::V6_vmpyiewuh_acc, dl, ResTy, in LowerHvxMulh()
1567 SDValue P = getInstr(Hexagon::V6_lvsplatw, dl, ResTy, in LowerHvxMulh()
1585 SDValue T3 = getInstr(Hexagon::V6_vadduhw, dl, PairTy, in LowerHvxMulh()
1732 SDValue Store = getInstr(StoreOpc, dl, MVT::Other, in LowerHvxMaskedOp()
1759 getInstr(StoreOpc, dl, MVT::Other, in LowerHvxMaskedOp()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp294 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
297 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
298 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
299 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
304 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
309 Pred.getInstr()->getDebugExpression()); in beginFunction()
316 if (IsDescribedByReg(I->getInstr())) in beginFunction()
318 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
325 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
327 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
H A DDbgEntityHistoryCalculator.cpp80 Entries.back().getInstr()->isIdenticalTo(MI)) { in startDbgValue()
82 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
96 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
198 const MachineInstr *StartMI = EI->getInstr(); in trimLocationRanges()
265 const MachineInstr *MI = Entry.getInstr(); in hasNonEmptyLocation()
339 if (Entry.getInstr()->isDebugEntryValue()) in clobberRegEntries()
341 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) { in clobberRegEntries()
344 for (auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
348 for (auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
379 const MachineInstr &DV = *Entry.getInstr(); in handleNewDebugValue()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp156 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
157 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
190 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
215 MachineInstr *MI = SU->getInstr(); in getAluKind()
289 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
318 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
320 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
389 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
438 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DGCNDPPCombine.cpp240 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
262 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { in createDPPInst()
272 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
273 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
288 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
291 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
292 return DPPInst.getInstr(); in createDPPInst()
486 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
H A DSIMachineScheduler.cpp319 RPTracker.setPos(SU->getInstr()); in initRegPressure()
400 TopRPTracker.setPos(SU->getInstr()); in schedule()
1127 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1151 if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr())) in colorExports()
1336 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1365 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1813 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1823 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1844 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
1932 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in schedule()
[all …]
H A DAMDGPUExportClustering.cpp30 return SIInstrInfo::isEXP(*SU.getInstr()); in isExport()
34 const MachineInstr *MI = SU->getInstr(); in isPositionExport()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
161 if (DAG->ExitSU.getInstr()) in apply()
169 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
188 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
H A DScheduleDAGInstrs.cpp264 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
292 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
396 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
445 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
516 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
550 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) { in addChainDependency()
1168 SU.getInstr()->dump(); in dumpNode()
1174 if (EntrySU.getInstr() != nullptr) in dump()
1178 if (ExitSU.getInstr() != nullptr) in dump()
1191 SU->getInstr()->print(oss, /*IsStandalone=*/true); in getGraphNodeLabel()
[all …]
H A DMachinePipeliner.cpp618 Cycles[SU->getInstr()] = Cycle; in schedule()
846 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
904 if (I.getInstr()->isPHI()) { in updatePhiDependences()
1369 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence()) in apply()
2053 SU->getInstr()->dump(); in schedulePipeline()
2397 SU->getInstr()->dump(); in insert()
2410 SU->getInstr()->dump(); in insert()
2680 if (UseSU->getInstr()->isPHI()) in isLoopCarried()
2918 if (SU->getInstr()->isPHI()) in finalizeSchedule()
2923 if (!SU->getInstr()->isPHI()) in finalizeSchedule()
[all …]
H A DSlotIndexes.cpp125 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
138 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
217 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
254 if (ILE.getInstr()) { in dump()
255 dbgs() << *ILE.getInstr(); in dump()
H A DMachineScheduler.cpp799 MachineInstr *MI = SU->getInstr(); in schedule()
949 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1185 if (EntrySU.getInstr() != nullptr) in dump()
1201 if (ExitSU.getInstr() != nullptr) in dump()
1408 MachineInstr *MI = SU->getInstr(); in scheduleMI()
1956 if (!SU.getInstr()->isCopy()) in apply()
3144 Cand.SU->getInstr(), in initCandidate()
3151 Cand.SU->getInstr(), in initCandidate()
3158 Cand.SU->getInstr(), in initCandidate()
3438 << *SU->getInstr()); in pickNode()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp373 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n'); in ExpandMOVX_RR()
376 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n"); in ExpandMOVX_RR()
388 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVSZX_RR()
419 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc); in ExpandMOVSZX_RR()
424 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
427 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
438 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and "); in ExpandMOVSZX_RM()
456 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandMOVSZX_RM()
474 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandPUSH_POP()
510 auto MI = MIB.getInstr(); in ExpandMOVEM()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp45 MachineInstr *MI = SU->getInstr(); in getHazardType()
88 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
183 MachineInstr &L0 = *SU->getInstr(); in getHazardType()
255 MachineInstr &MI = *SU->getInstr(); in EmitInstruction()
H A DMVETPAndVPTOptimisationsPass.cpp251 LLVM_DEBUG(dbgs() << "Lowered WhileLoopStart into: " << *MI.getInstr()); in LowerWhileLoopStart()
409 LLVM_DEBUG(dbgs() << "Merged LoopDec and End into: " << *MI.getInstr()); in MergeLoopEnd()
509 << *MI.getInstr()); in ConvertTailPredLoop()
615 MIBuilder.getInstr()->dump()); in ReplaceRegisterUseWithVPNOT()
617 return *MIBuilder.getInstr(); in ReplaceRegisterUseWithVPNOT()
864 MIBuilder.getInstr()->dump(); dbgs() << " Removed VCMP: "; in ReplaceVCMPsByVPNOTs()
998 dbgs() << " with VMOVT: "; MIBuilder.getInstr()->dump()); in ConvertVPSEL()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSlotIndexes.h53 MachineInstr* getInstr() const { return mi; } in getInstr() function
404 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
413 if (I->getInstr())
598 assert(miEntry->getInstr() == &MI &&
H A DScheduleDAG.h373 MachineInstr *getInstr() const { in getInstr() function
387 ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0); in addPredBarrier()
582 if (SU->isInstr()) return &SU->getInstr()->getDesc(); in getInstrDesc()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFixIrreducibleControlFlow.cpp382 unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; in makeSingleEntryLoop()
479 MIB.addMBB(MIB.getInstr() in makeSingleEntryLoop()
480 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1) in makeSingleEntryLoop()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp437 .getInstr(); in loadImmediate()
441 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); in loadImmediate()
449 .getInstr(); in loadImmediate()

1234