617       OrderedInsts.push_back(SU->getInstr());  in schedule()
618       Cycles[SU->getInstr()] = Cycle;  in schedule()
619       Stages[SU->getInstr()] = Schedule.stageScheduled(SU);  in schedule()
745     MachineInstr &MI = *SU.getInstr();  in addLoopCarriedDependences()
770           MachineInstr &LdMI = *Load->getInstr();  in addLoopCarriedDependences()
846     MachineInstr *MI = I.getInstr();  in updatePhiDependences()
902       MachineInstr *PMI = PI.getSUnit()->getInstr();  in updatePhiDependences()
904         if (I.getInstr()->isPHI()) {  in updatePhiDependences()
927     if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase,  in changeDependences()
932     Register OrigBase = I.getInstr()->getOperand(BasePos).getReg();  in changeDependences()
1243           (SI.getKind() == SDep::Anti && !SI.getSUnit()->getInstr()->isPHI()))  in createAdjacencyStructure()
1254       if (!SUnits[i].getInstr()->mayStore() ||  in createAdjacencyStructure()
1257       if (PI.getKind() == SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) {  in createAdjacencyStructure()
1369     if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence())  in apply()
1379       MachineInstr *TmpMI = TmpSU->getInstr();  in apply()
1403         MachineInstr *TmpMI = TmpSU->getInstr();  in apply()
1613     const MachineInstr *MI = SU->getInstr();  in computeLiveOuts()
1628     for (const MachineOperand &MO : SU->getInstr()->operands())  in computeLiveOuts()
1669       MachineBasicBlock::const_iterator CurInstI = SU->getInstr();  in registerPressureFilter()
1674       RecRPTracker.getMaxUpwardPressureDelta(SU->getInstr(), nullptr, RPDelta,  in registerPressureFilter()
2053         SU->getInstr()->dump();  in schedulePipeline()
2076         if (SU->getInstr()->isPHI())  in schedulePipeline()
2290   MachineInstr *SI = Source->getInstr();  in isLoopCarriedDep()
2291   MachineInstr *DI = Dep.getSUnit()->getInstr();  in isLoopCarriedDep()
2386         if (ST.getInstrInfo()->isZeroCost(CI->getInstr()->getOpcode()))  in insert()
2388         assert(ProcItinResources.canReserveResources(*CI->getInstr()) &&  in insert()
2390         ProcItinResources.reserveResources(*CI->getInstr());  in insert()
2393     if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()) ||  in insert()
2394         ProcItinResources.canReserveResources(*SU->getInstr())) {  in insert()
2397         SU->getInstr()->dump();  in insert()
2410       SU->getInstr()->dump();  in insert()
2467     if (DAG->isBackedge(SU, P) && P.getSUnit()->getInstr()->isPHI())  in multipleIterations()
2469         if (S.getKind() == SDep::Data && S.getSUnit()->getInstr()->isPHI())  in multipleIterations()
2508         if (BE && Dep.getSUnit() == BE && !SU->getInstr()->isPHI() &&  in computeStart()
2539   MachineInstr *MI = SU->getInstr();  in orderDependence()
2563           (*I)->getInstr()->readsWritesVirtualRegister(Reg);  in orderDependence()
2595                  isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {  in orderDependence()
2680   if (UseSU->getInstr()->isPHI())  in isLoopCarried()
2784       if (!PredSU->getInstr()->isPHI() && PredIndex < Index) {  in checkValidNodeOrder()
2800       if (!SuccSU->getInstr()->isPHI() && SuccIndex < Index) {  in checkValidNodeOrder()
2807     if (PredBefore && SuccBefore && !SU->getInstr()->isPHI()) {  in checkValidNodeOrder()
2841     MachineInstr *MI = SU->getInstr();  in fixupRegisterOverlaps()
2909     SSD->applyInstrChange(SU->getInstr(), *this);  in finalizeSchedule()
2918       if (SU->getInstr()->isPHI())  in finalizeSchedule()
2923       if (!SU->getInstr()->isPHI())  in finalizeSchedule()
2939     os << "   SU(" << I->NodeNum << ") " << *(I->getInstr());  in print()
2953       CI->getInstr()->print(os);  in print()