| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm() 373 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 389 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 401 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 483 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 512 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select() 598 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 702 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 757 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 871 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() [all …]
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| H A D | MipsISelLowering.cpp | 1631 Register ScrReg = RegInfo.createVirtualRegister(RC); in emitSignExtendToI32InReg() 1662 Register Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1663 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1664 Register Incr2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1666 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1786 Register Off = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1857 Register Scratch = MRI.createVirtualRegister(RC); in emitAtomicCmpSwap() 1911 Register Mask = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() 1912 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() 1973 Register Off = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() [all …]
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| H A D | MipsMachineFunction.cpp | 50 MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); in getGlobalBaseReg() 76 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() 77 Register V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| H A D | Mips16ISelDAGToDAG.cpp | 78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() 79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() 80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| H A D | MipsSEISelLowering.cpp | 3067 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() 3073 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() 3136 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() 3142 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() 3190 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW() 3253 Register Wt = RegInfo.createVirtualRegister( in emitINSERT_FW() 3447 Register Wt1 = RegInfo.createVirtualRegister( in emitFILL_FW() 3450 Register Wt2 = RegInfo.createVirtualRegister( in emitFILL_FW() 3580 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO() 3822 Register Ws1 = RegInfo.createVirtualRegister(RC); in emitFEXP2_W_1() [all …]
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| H A D | MipsSEFrameLowering.cpp | 174 Register VR = MRI.createVirtualRegister(RC); in expandLoadCCond() 189 Register VR = MRI.createVirtualRegister(RC); in expandStoreCCond() 207 Register VR0 = MRI.createVirtualRegister(RC); in expandLoadACC() 208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() 232 Register VR0 = MRI.createVirtualRegister(RC); in expandStoreACC() 233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() 265 Register VR0 = MRI.createVirtualRegister(RC); in expandCopyACC() 266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() 541 Register VR = MF.getRegInfo().createVirtualRegister(RC); in emitPrologue()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 447 PS->PoisonReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction() 480 PS->InitialReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction() 1535 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() 1555 Register PredStateReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() 1556 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() 1663 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() 1684 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() 1714 Register VStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() 1936 Register NewReg = MRI->createVirtualRegister(RC); in hardenValueInRegister() 2127 ExpectedRetAddrReg = MRI->createVirtualRegister(AddrRC); in tracePredStateThroughCall() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 279 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() 289 Register BasePtr = MRI.createVirtualRegister(PtrRC); in emitPrologue() 296 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() 304 Register BitmaskReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() 348 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() 354 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
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| H A D | WebAssemblyPeephole.cpp | 66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop() 123 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
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| H A D | WebAssemblyRegisterInfo.cpp | 123 Register OffsetOp = MRI.createVirtualRegister(PtrRC); in eliminateFrameIndex() 128 FIRegOperand = MRI.createVirtualRegister(PtrRC); in eliminateFrameIndex()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 238 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64() 358 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() 359 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() 1687 Register TmpReg = MRI->createVirtualRegister( in selectImageIntrinsic() 2188 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() 2189 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() 2422 Register TmpReg = MRI->createVirtualRegister( in selectG_AMDGPU_ATOMIC_CMPXCHG() 2569 Register HiReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() 2570 Register LoReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() 2592 MaskedLo = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() [all …]
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| H A D | SIInstrInfo.cpp | 1061 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() 2668 Register DstElt = MRI.createVirtualRegister(EltRC); in insertSelect() 4592 Register Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove() 4607 Register SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg() 4995 Register DstReg = MRI.createVirtualRegister(SRC); in readlaneVGPRToSGPR() 5000 Register NewSrcReg = MRI.createVirtualRegister(VRC); in readlaneVGPRToSGPR() 5167 Register DstReg = MRI.createVirtualRegister(DstRC); in legalizeGenericOperand() 5271 Register SRsrc = MRI.createVirtualRegister(SRsrcRC); in emitLoadSRsrcFromVGPRLoop() 6118 NewDstReg = MRI.createVirtualRegister(NewDstRC); in moveToVALU() 6212 Register CopySCC = MRI.createVirtualRegister(TC); in lowerSelect() [all …]
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| H A D | SILoadStoreOptimizer.cpp | 1079 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair() 1091 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeRead2Pair() 1185 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeWrite2Pair() 1223 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair() 1277 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair() 1329 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair() 1390 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair() 1459 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferStorePair() 1614 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeBufferStorePair() 1695 Register CarryReg = MRI->createVirtualRegister(CarryRC); in computeBase() [all …]
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| H A D | SIOptimizeVGPRLiveRange.cpp | 479 Register NewReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() 480 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() 520 Register NewReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange() 521 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | SwiftErrorValueTracking.cpp | 37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg() 59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt() 133 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in createEntriesInEntryBlock() 243 UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC); in propagateVRegs()
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| H A D | MIRVRegNamerUtils.cpp | 139 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) { in createVirtualRegister() function in VRegRenamer 170 return RC ? MRI.createVirtualRegister(RC, LowerName) in createVirtualRegisterWithLowerName()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCopyPhysRegs.cpp | 90 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB() 100 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 207 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex() 232 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex() 254 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex() 275 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVExtract.cpp | 71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad() 90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad() 125 Register AddrR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in runOnMachineFunction()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 656 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc() 745 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca() 753 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca() 762 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca() 770 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca() 878 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling() 923 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore() 1037 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRBitSpilling() 1477 Register SRegHi = MF.getRegInfo().createVirtualRegister(RC), in eliminateFrameIndex() 1478 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() [all …]
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| H A D | PPCVSXCopy.cpp | 105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock() 127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 420 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane() 435 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg() 449 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass); in createRegSequence() 467 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createVExt() 479 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass); in createInsertSubreg() 495 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createImplicitDef()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 178 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg() 254 VRBase = MRI->createVirtualRegister(RC); in CreateVirtualRegisters() 282 Register VReg = MRI->createVirtualRegister(RC); in getVR() 329 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand() 396 Register NewVReg = MRI->createVirtualRegister(IIRC); in AddOperand() 465 Register NewReg = MRI->createVirtualRegister(RC); in ConstrainForSubReg() 522 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode() 536 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode() 574 VRBase = MRI->createVirtualRegister(SRC); in EmitSubregNode() 615 Register NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 1809 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareMBB() 1810 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareMBB() 1811 Register Result = MRI.createVirtualRegister(RC); in prepareMBB() 1859 Register Result = MRI.createVirtualRegister(RC); in prepareSymbol() 1916 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() 1917 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareSymbol() 2278 Register IReg = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() 2301 Register BReg = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() 2302 Register Tmp1 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() 2303 Register Tmp2 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 343 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction() 349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction() 357 Register Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
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