150         Register MaskedReg = MRI->createVirtualRegister(SrcRC);  in selectCOPY()
238   Register DstReg = MRI->createVirtualRegister(&SubRC);  in getSubOperand64()
335     Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass());  in selectG_ADD_SUB()
358   Register DstLo = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
359   Register DstHi = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
370     Register CarryReg = MRI->createVirtualRegister(CarryRC);  in selectG_ADD_SUB()
377       .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead)  in selectG_ADD_SUB()
801   Register InterpMov = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectInterpP1F16()
1401     Register M0Base = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectDSGWSIntrinsic()
1420       Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectDSGWSIntrinsic()
1423           MRI->createVirtualRegister(&AMDGPU::VReg_64_Align2RegClass);  in selectDSGWSIntrinsic()
1687       Register TmpReg = MRI->createVirtualRegister(  in selectImageIntrinsic()
1742     Register Zero = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectImageIntrinsic()
1756       Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectImageIntrinsic()
1914     Register LoReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1915     Register HiReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1935       Register TmpReg0 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1936       Register TmpReg1 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1937       Register ImmReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2044     Register UndefReg = MRI->createVirtualRegister(SrcRC);  in selectG_SZA_EXT()
2102       Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);  in selectG_SZA_EXT()
2103       Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SZA_EXT()
2188     Register LoReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2189     Register HiReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2243   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2244   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2245   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2246   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2280   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2281   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2282   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2283   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2422   Register TmpReg = MRI->createVirtualRegister(  in selectG_AMDGPU_ATOMIC_CMPXCHG()
2569   Register HiReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2570   Register LoReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2591     Register MaskLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2592     MaskedLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2605     Register MaskHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2606     MaskedHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2946       Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SHUFFLE_VECTOR()
3021     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());  in selectAMDGPU_BUFFER_ATOMIC_FADD()
3478   Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSmrdSgpr()
3596                 MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
3665   Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
3722       SAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectScratchSAddr()
3749     Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectMUBUFScratchOffen()
3996   Register RSrc2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
3997   Register RSrc3 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
3998   Register RSrcHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
3999   Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);  in buildRSRC()
4020     RSrcLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
4105   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in splitIllegalMUBUFOffset()