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Searched refs:PredReg (Results 1 – 25 of 27) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp557 .addReg(PredReg); in UpdateBaseRegUses()
578 .addReg(PredReg); in UpdateBaseRegUses()
905 Register PredReg; in MergeOpsUpdate() local
1210 MIPredReg != PredReg) in isIncrementOrDecrement()
1294 Register PredReg; in MergeBaseUpdateLSMultiple() local
1490 Register PredReg; in MergeBaseUpdateLoadStore() local
1628 Register PredReg; in MergeBaseUpdateLSDouble() local
1798 Register PredReg; in FixInvalidRegPairOp() local
1898 Register PredReg; in LoadStoreMultipleOpti() local
2524 Register PredReg; in RescheduleLoadStoreInstrs() local
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H A DThumb2InstrInfo.h78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
84 Register &PredReg);
86 Register PredReg; in getVPTInstrPredicate() local
87 return getVPTInstrPredicate(MI, PredReg); in getVPTInstrPredicate()
H A DThumb2InstrInfo.cpp73 Register PredReg; in ReplaceTailWithBranchTo() local
74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
121 Register PredReg; in isLegalToSplitMBBAt() local
122 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
318 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
330 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
539 Register PredReg; in rewriteT2FrameIndex() local
754 Register &PredReg) { in getITInstrPredicate() argument
758 return getInstrPredicate(MI, PredReg); in getITInstrPredicate()
778 PredReg = 0; in getVPTInstrPredicate()
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H A DMVEVPTBlockPass.cpp106 Register PredReg; in StepOverPredicatedInstrs() local
116 NextPred = getVPTInstrPredicate(*Iter, PredReg); in StepOverPredicatedInstrs()
251 Register PredReg; in InsertVPTBlocks() local
254 ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg); in InsertVPTBlocks()
H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
77 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
113 PredReg, MIFlags); in emitLoadConstPool()
116 PredReg, MIFlags); in emitLoadConstPool()
H A DThumb2SizeReduction.cpp471 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
484 .addReg(PredReg) in ReduceLoadStore()
689 Register PredReg; in ReduceSpecial() local
690 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
731 Register PredReg; in ReduceSpecial() local
733 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) in ReduceSpecial()
802 Register PredReg; in ReduceTo2Addr() local
803 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
895 Register PredReg; in ReduceToNarrow() local
896 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
295 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
307 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
H A DThumbRegisterInfo.h43 Register PredReg = Register(),
H A DThumb2ITBlockPass.cpp202 Register PredReg; in InsertITInstructions() local
203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
H A DARMBaseRegisterInfo.cpp486 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
498 .add(predOps(Pred, PredReg)) in emitLoadConstPool()
835 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
849 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
853 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
H A DARMBaseInstrInfo.h542 unsigned PredReg = 0) {
544 MachineOperand::CreateReg(PredReg, false)}};
762 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
778 ARMCC::CondCodes Pred, Register PredReg,
785 ARMCC::CondCodes Pred, Register PredReg,
H A DARMFrameLowering.cpp279 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate() argument
282 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
285 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
293 unsigned PredReg = 0) { in emitSPUpdate() argument
295 MIFlags, Pred, PredReg); in emitSPUpdate()
2347 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr() local
2366 Pred, PredReg); in eliminateCallFramePseudoInstr()
2370 Pred, PredReg); in eliminateCallFramePseudoInstr()
2377 MachineInstr::NoFlags, Pred, PredReg); in eliminateCallFramePseudoInstr()
H A DARMConstantIslandPass.cpp1410 Register PredReg; in createNewWater() local
1413 getITInstrPredicate(*I, PredReg) != ARMCC::AL; in createNewWater()
1456 Register PredReg; in createNewWater() local
1457 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in createNewWater()
1480 Register PredReg; in createNewWater() local
1481 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL); in createNewWater()
1885 Register PredReg; in optimizeThumb2Branches() local
1887 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg); in optimizeThumb2Branches()
H A DARMBaseRegisterInfo.h190 Register PredReg = Register(),
H A DARMISelDAGToDAG.cpp1747 SDValue PredReg; in tryMVEIndexedLoad() local
1765 PredReg = CurDAG->getRegister(0, MVT::i32); in tryMVEIndexedLoad()
1781 PredReg = LD->getMask(); in tryMVEIndexedLoad()
2911 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in SelectCDE_CXxD() local
2913 Ops.push_back(PredReg); in SelectCDE_CXxD()
4263 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4264 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
4286 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4287 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
4308 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
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H A DARMBaseInstrInfo.cpp2211 Register &PredReg) { in getInstrPredicate() argument
2214 PredReg = 0; in getInstrPredicate()
2218 PredReg = MI.getOperand(PIdx+1).getReg(); in getInstrPredicate()
2241 Register PredReg; in commuteInstructionImpl() local
2242 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2244 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2446 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate() argument
2452 .add(predOps(Pred, PredReg)) in emitARMRegPlusImmediate()
2476 .add(predOps(Pred, PredReg)) in emitARMRegPlusImmediate()
5489 Register PredReg; in findCMPToFoldIntoCBZ() local
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp177 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
179 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
180 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); in getCompoundOp()
187 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
189 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
191 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
193 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
H A DHexagonMCChecker.cpp66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg() argument
70 PredReg = R; in initReg()
75 NewPreds.insert(PredReg); in initReg()
91 unsigned PredReg = Hexagon::NoRegister; in init() local
97 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue); in init()
99 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue); in init()
127 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
182 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
H A DHexagonMCChecker.h81 void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
477 PredReg = MCI.getOperand(1).getReg(); // P0 in getDuplexCandidateGroup()
479 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) { in getDuplexCandidateGroup()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp121 bool isScalarPred(RegisterSubReg PredReg);
323 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred() argument
325 WorkQ.push(PredReg); in isScalarPred()
H A DHexagonInstrInfo.h428 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
462 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
H A DHexagonInstrInfo.cpp1614 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
1615 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); in PredicateInstruction()
1618 T.addReg(PredReg, PredRegFlags); in PredicateInstruction()
1632 MRI.clearKillFlags(PredReg); in PredicateInstruction()
3131 unsigned PredReg) const { in predCanBeUsedAsDotNew()
3134 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg)) in predCanBeUsedAsDotNew()
3136 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) in predCanBeUsedAsDotNew()
4442 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg() argument
4450 PredReg = Cond[1].getReg(); in getPredReg()
H A DHexagonHardwareLoops.cpp648 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
649 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) in getLoopTripCount()
651 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h356 unsigned PredReg,

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