173                            ARMCC::CondCodes Pred, unsigned PredReg);
177         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
183         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
488                                         unsigned PredReg) {  in UpdateBaseRegUses()  argument
557           .addReg(PredReg);  in UpdateBaseRegUses()
578         .addReg(PredReg);  in UpdateBaseRegUses()
628     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreMulti()  argument
748               .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
759             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
765             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
770           .add(predOps(Pred, PredReg))  in CreateLoadStoreMulti()
815       UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);  in CreateLoadStoreMulti()
822   MIB.addImm(Pred).addReg(PredReg);  in CreateLoadStoreMulti()
835     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreDouble()  argument
852   MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in CreateLoadStoreDouble()
905   Register PredReg;  in MergeOpsUpdate()  local
906   ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);  in MergeOpsUpdate()
911                                    Opcode, Pred, PredReg, DL, Regs,  in MergeOpsUpdate()
915                                   Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);  in MergeOpsUpdate()
1189                                   ARMCC::CondCodes Pred, Register PredReg) {  in isIncrementOrDecrement()  argument
1210       MIPredReg != PredReg)  in isIncrementOrDecrement()
1221                  ARMCC::CondCodes Pred, Register PredReg, int &Offset) {  in findIncDecBefore()  argument
1234   Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);  in findIncDecBefore()
1241                 ARMCC::CondCodes Pred, Register PredReg, int &Offset,  in findIncDecAfter()  argument
1254     unsigned Off = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);  in findIncDecAfter()
1294   Register PredReg;  in MergeBaseUpdateLSMultiple()  local
1295   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLSMultiple()
1310     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLSMultiple()
1317     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLSMultiple()
1350     .addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSMultiple()
1490   Register PredReg;  in MergeBaseUpdateLoadStore()  local
1491   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLoadStore()
1497     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLoadStore()
1504     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLoadStore()
1532                    .addReg(PredReg)  in MergeBaseUpdateLoadStore()
1548                 .addReg(PredReg)  in MergeBaseUpdateLoadStore()
1560                 .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1572               .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1590                      .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1600                      .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1628   Register PredReg;  in MergeBaseUpdateLSDouble()  local
1629   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLSDouble()
1634                                                             PredReg, Offset);  in MergeBaseUpdateLSDouble()
1639     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLSDouble()
1658      .addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSDouble()
1735                           unsigned PredReg, const TargetInstrInfo *TII,  in InsertLDR_STR()  argument
1742     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1751     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1798   Register PredReg;  in FixInvalidRegPairOp()  local
1799   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in FixInvalidRegPairOp()
1810         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1818         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1841                     false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);  in FixInvalidRegPairOp()
1843                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1857                     EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1860                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1898       Register PredReg;  in LoadStoreMultipleOpti()  local
1899       ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);  in LoadStoreMultipleOpti()
2173                           Register &BaseReg, int &Offset, Register &PredReg,
2259     Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {  in CanFormLdStDWord()  argument
2322   Pred = getInstrPredicate(*Op0, PredReg);  in CanFormLdStDWord()
2422         Register BaseReg, PredReg;  in RescheduleOps()  local
2430                                              Offset, PredReg, Pred, isT2)) {  in RescheduleOps()
2450             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2464             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2524       Register PredReg;  in RescheduleLoadStoreInstrs()  local
2525       if (getInstrPredicate(MI, PredReg) != ARMCC::AL)  in RescheduleLoadStoreInstrs()
2892     Register PredReg;  in DistributeIncrements()  local
2894         getInstrPredicate(*Increment, PredReg) != ARMCC::AL)  in DistributeIncrements()