| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsOptionRecord.h | 48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord() 67 const MCRegisterClass *GPR64RegClass; variable
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| H A D | MipsMachineFunction.cpp | 42 return Mips::GPR64RegClass; in getGlobalBaseRegClass() 74 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg() 154 ? Mips::GPR64RegClass in createEhDataRegsFI()
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| H A D | MipsSERegisterInfo.cpp | 59 return &Mips::GPR64RegClass; in intRegClass() 223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
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| H A D | MipsSEInstrInfo.cpp | 149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg() 150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg() 159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg() 256 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack() 334 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack() 628 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
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| H A D | MipsSEFrameLowering.cpp | 422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue() 720 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue() 895 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves() 911 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
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| H A D | MipsSubtarget.cpp | 229 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass in getCriticalPathRCs()
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| H A D | MipsRegisterInfo.cpp | 54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
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| H A D | MipsSEISelLowering.cpp | 71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering() 3339 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX() 3525 : &Mips::GPR64RegClass); in emitST_F16_PSEUDO() 3531 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); in emitST_F16_PSEUDO() 3577 : &Mips::GPR64RegClass); in emitLD_F16_PSEUDO() 3669 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO() 3773 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPEXTEND_PSEUDO()
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| H A D | MipsISelLowering.cpp | 4129 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint() 4153 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint() 4815 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitLDR_D() 4950 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitSTR_D()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMIChecking.cpp | 107 const MCRegisterClass *GPR64RegClass = in hasLiveDefs() local 118 RegIsGPR64 = GPR64RegClass->contains(MO.getReg()); in hasLiveDefs()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 411 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP() 472 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV() 1715 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs() 1817 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad() 1831 RC = &AArch64::GPR64RegClass; in emitLoad() 2670 RC = &AArch64::GPR64RegClass; in selectSelect() 2962 RC = &AArch64::GPR64RegClass; in fastLowerArguments() 3224 CallReg = createResultReg(&AArch64::GPR64RegClass); in fastLowerCall() 4745 case MVT::i64: RC = &AArch64::GPR64RegClass; break; in selectBitCast() 4838 RC = &AArch64::GPR64RegClass; in selectSDiv() [all …]
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| H A D | AArch64AdvSIMDScalarPass.cpp | 109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64() 110 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
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| H A D | AArch64CleanupLocalDynamicTLSPass.cpp | 126 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
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| H A D | AArch64RegisterInfo.cpp | 378 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass() 606 &AArch64::GPR64RegClass); in createScratchRegisterForInstruction() 695 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
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| H A D | AArch64FrameLowering.cpp | 610 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister() 2290 if (AArch64::GPR64RegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs() 2309 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs() 2767 if (AArch64::GPR64RegClass.contains(Reg) || in determineCalleeSaves() 2773 if (AArch64::GPR64RegClass.contains(Reg) && in determineCalleeSaves() 2787 if (AArch64::GPR64RegClass.contains(PairedReg) && in determineCalleeSaves() 2872 const TargetRegisterClass &RC = AArch64::GPR64RegClass; in determineCalleeSaves() 3178 Register ScratchReg = MRI->createVirtualRegister(&AArch64::GPR64RegClass); in emitUnrolled() 3215 : MRI->createVirtualRegister(&AArch64::GPR64RegClass); in emitLoop() 3216 Register SizeReg = MRI->createVirtualRegister(&AArch64::GPR64RegClass); in emitLoop()
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| H A D | AArch64InstrInfo.cpp | 748 RC = &AArch64::GPR64RegClass; in insertSelect() 4043 &AArch64::GPR64RegClass); in emitFrameOffsetAdj() 4245 SpillRC = &AArch64::GPR64RegClass; in foldMemoryOperandImpl() 5284 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence() 5299 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence() 5325 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence() 5367 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence() 5391 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence() 5417 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence() 6411 for (unsigned Reg : AArch64::GPR64RegClass) { in findRegisterToSaveLRTo() [all …]
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| H A D | AArch64CollectLOH.cpp | 506 for (MCPhysReg Reg : AArch64::GPR64RegClass) in handleNormalInst()
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| H A D | AArch64FalkorHWPFFix.cpp | 751 for (unsigned ScratchReg : AArch64::GPR64RegClass) { in runOnLoop()
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| H A D | AArch64LoadStoreOptimizer.cpp | 1144 LdRt, AArch64::sub_32, &AArch64::GPR64RegClass)) in promoteLoadFromStore()
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| H A D | AArch64ISelLowering.cpp | 5158 RC = &AArch64::GPR64RegClass; in LowerFormalArguments() 5326 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in LowerFormalArguments() 5410 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); in saveVarArgRegisters() 6340 if (AArch64::GPR64RegClass.contains(*I)) in LowerReturn() 7918 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); in LowerRETURNADDR() 17696 if (AArch64::GPR64RegClass.contains(*I)) in insertCopiesSplitCSR() 17697 RC = &AArch64::GPR64RegClass; in insertCopiesSplitCSR()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsOptionRecord.cpp | 81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 492 : &AArch64::GPR64RegClass; in getRegClassForTypeOnBank() 526 : &AArch64::GPR64RegClass; in getMinClassForRegBank() 1950 RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI); in preISelLower() 1977 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower() 2183 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect() 2971 SrcRC == &AArch64::GPR64RegClass) { in select() 3149 {&AArch64::GPR64RegClass}, {}) in select() 3815 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues() 4320 auto RC = Is32Bit ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass; in emitCMN() 5164 RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI); in selectIntrinsic() [all …]
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| H A D | AArch64LegalizerInfo.cpp | 914 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue() 936 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue() 1246 auto Scratch = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in legalizeAtomicCmpxchg128()
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| H A D | AArch64CallLowering.cpp | 489 Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in handleMustTailForwardedRegisters()
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