378   const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass  in materializeInt()
411         &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in materializeFP()
472       ResultReg = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
485     unsigned Result64 = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
1301       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rr()
1344     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_ri()
1387       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rs()
1429     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rx()
1715     RC = &AArch64::GPR64RegClass;  in emitLogicalOp_rs()
1817              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1822              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1827              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1831     RC = &AArch64::GPR64RegClass;  in emitLoad()
1859     unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);  in emitLoad()
2670     RC = &AArch64::GPR64RegClass;  in selectSelect()
2829       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2962       RC = &AArch64::GPR64RegClass;  in fastLowerArguments()
3224       CallReg = createResultReg(&AArch64::GPR64RegClass);  in fastLowerCall()
3416     Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in fastLowerIntrinsicCall()
3427       DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,  in fastLowerIntrinsicCall()
3939       Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emiti1Ext()
3972       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitMul_rr()
3980   return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,  in emitSMULL_rr()
3988   return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,  in emitUMULL_rr()
4006       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_rr()
4031       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_ri()
4108       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_rr()
4134       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_ri()
4224       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_rr()
4250       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_ri()
4362     Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emitIntExt()
4372       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4459     unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);  in optimizeIntExtLoad()
4502         unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);  in selectIntExt()
4555       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()
4745   case MVT::i64: RC = &AArch64::GPR64RegClass; break;  in selectBitCast()
4838     RC = &AArch64::GPR64RegClass;  in selectSDiv()
4979     ResRC = &AArch64::GPR64RegClass;  in selectAtomicCmpXchg()