| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1209 MVT DestVT = VA.getLocVT(); in processCallArgs() local 1217 MVT DestVT = VA.getLocVT(); in processCallArgs() local 1750 MVT DestVT = VA.getValVT(); in selectRet() local 1752 if (RVVT != DestVT) { in selectRet() 1782 EVT SrcVT, DestVT; in selectTrunc() local 1788 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in selectTrunc() 1820 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt() local 1865 if ((DestVT != MVT::i32) && (DestVT != MVT::i16)) in emitIntSExt() 1900 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) || in emitIntExt() 1920 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem() local [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 233 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local 234 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n"; in EmitAction() 235 if (MVT(DestVT).isFloatingPoint()) { in EmitAction() 247 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local 248 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction() 249 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1272 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp() 1440 MVT DestVT = VA.getLocVT(); in processCallArgs() local 1446 ArgVT = DestVT; in processCallArgs() 1452 MVT DestVT = VA.getLocVT(); in processCallArgs() local 1458 ArgVT = DestVT; in processCallArgs() 1507 MVT DestVT = VA.getValVT(); in finishCall() local 1508 MVT CopyVT = DestVT; in finishCall() 1759 if (RVVT != DestVT) { in SelectRet() 1808 if (DestVT != MVT::i32 && DestVT != MVT::i64) in PPCEmitIntExt() 1828 } else if (DestVT == MVT::i32) { in PPCEmitIntExt() [all …]
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| H A D | PPCISelLowering.h | 988 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
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| H A D | PPCISelLowering.cpp | 8905 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp() 8906 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp() 8914 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument 8915 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp() 8916 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp() 8924 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument 8925 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp() 8926 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp() 16233 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument 16234 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFree() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2804 MVT DestVT; in selectFPToInt() local 2805 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt() 2837 MVT DestVT; in selectIntToFP() local 2844 assert((DestVT == MVT::f32 || DestVT == MVT::f64) && in selectIntToFP() 3878 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 && in selectTrunc() 3926 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 || in emiti1Ext() 3930 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emiti1Ext() 4323 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && in emitIntExt() 4324 (DestVT != MVT::i32) && (DestVT != MVT::i64)) || in emitIntExt() 4359 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emitIntExt() [all …]
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| H A D | AArch64ISelLowering.cpp | 8618 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local 8625 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8645 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8651 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8656 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8659 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8670 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle() 16894 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in PerformDAGCombine() local 16897 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds); in PerformDAGCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1738 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp() 1950 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local 1953 ArgVT = DestVT; in ProcessCallArgs() 1959 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local 1962 ArgVT = DestVT; in ProcessCallArgs() 2125 MVT DestVT = VA.getValVT(); in SelectRet() local 2127 if (RVVT != DestVT) { in SelectRet() 2582 EVT SrcVT, DestVT; in SelectTrunc() local 2588 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectTrunc() 2602 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) in ARMEmitIntExt() [all …]
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| H A D | ARMISelLowering.cpp | 7994 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local 8002 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8018 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8024 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8029 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8032 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle() 8035 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 878 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local 1704 unsigned DestSize = DestVT.getSizeInBits(); in EmitStackConvert() 2285 EVT DestVT = Node->getValueType(0); in ExpandLegalINT_TO_FP() local 2294 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP() 2297 DestVT))) { in ExpandLegalINT_TO_FP() 2344 if (DestVT != Sub.getValueType()) { in ExpandLegalINT_TO_FP() 2469 if (DestVT == MVT::f32) in ExpandLegalINT_TO_FP() 2504 EVT DestVT = N->getValueType(0); in PromoteLegalINT_TO_FP() local 2550 DAG.getNode(OpToUse, dl, DestVT, in PromoteLegalINT_TO_FP() 2565 EVT DestVT = N->getValueType(0); in PromoteLegalFP_TO_INT() local [all …]
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| H A D | LegalizeTypes.cpp | 887 EVT DestVT) { in CreateStackStoreLoad() argument 894 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false); in CreateStackStoreLoad() 903 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align); in CreateStackStoreLoad()
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| H A D | SelectionDAGBuilder.cpp | 3210 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp() 3386 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); in visitTrunc() 3412 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitFPTrunc() local 3413 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, in visitFPTrunc() 3423 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); in visitFPExt() 3468 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT); in visitPtrToInt() 3477 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitIntToPtr() local 3480 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT); in visitIntToPtr() 3492 if (DestVT != N.getValueType()) in visitBitCast() 3494 DestVT, N)); // convert types. in visitBitCast() [all …]
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| H A D | LegalizeVectorTypes.cpp | 374 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local 392 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags()); in ScalarizeVecRes_UnaryOp() 1941 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local 1943 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp() 1959 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
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| H A D | LegalizeTypes.h | 220 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2565 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local 2570 if (DestVT == MVT::f16) in LowerUINT_TO_FP() 2592 if (DestVT == MVT::f32) in LowerUINT_TO_FP() 2595 assert(DestVT == MVT::f64); in LowerUINT_TO_FP() 2601 EVT DestVT = Op.getValueType(); in LowerSINT_TO_FP() local 2607 if (DestVT == MVT::f16) in LowerSINT_TO_FP() 2632 if (DestVT == MVT::f32) in LowerSINT_TO_FP() 2635 assert(DestVT == MVT::f64); in LowerSINT_TO_FP() 2816 EVT DestVT = Op.getValueType(); in LowerFP_TO_INT() local 4025 if (DestVT.isVector()) { in PerformDAGCombine() [all …]
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| H A D | SIISelLowering.h | 251 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
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| H A D | SIISelLowering.cpp | 907 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument 910 DestVT.getScalarType() == MVT::f32 && in isFPExtFoldable()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1141 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local 1142 RegisterVT = DestVT; in getVectorTypeBreakdownMVT() 1143 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT() 1144 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); in getVectorTypeBreakdownMVT() 1605 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local 1606 RegisterVT = DestVT; in getVectorTypeBreakdown() 1608 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown() 1613 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2268 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument 2269 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType() 2274 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument 2276 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType() 2679 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument 2680 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree() 2689 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument 2690 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable() 2692 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 19848 MVT DestVT = Cast.getSimpleValueType(); in vectorizeExtractedCast() local 19858 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM); in vectorizeExtractedCast() 19878 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast, in vectorizeExtractedCast() 24227 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT; in LowerEXTEND_VECTOR_INREG() local 24229 unsigned DestWidth = DestVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG() 24233 unsigned DestElts = DestVT.getVectorNumElements(); in LowerEXTEND_VECTOR_INREG() 24242 Curr = DAG.getBitcast(DestVT, Curr); in LowerEXTEND_VECTOR_INREG() 24245 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()
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