966 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()
973   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;  in isNarrowingProfitable()
2565   EVT DestVT = Op.getValueType();  in LowerUINT_TO_FP()  local
2570     if (DestVT == MVT::f16)  in LowerUINT_TO_FP()
2576     return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);  in LowerUINT_TO_FP()
2581   if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {  in LowerUINT_TO_FP()
2592   if (DestVT == MVT::f32)  in LowerUINT_TO_FP()
2595   assert(DestVT == MVT::f64);  in LowerUINT_TO_FP()
2601   EVT DestVT = Op.getValueType();  in LowerSINT_TO_FP()  local
2607     if (DestVT == MVT::f16)  in LowerSINT_TO_FP()
2613     return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext);  in LowerSINT_TO_FP()
2620   if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {  in LowerSINT_TO_FP()
2632   if (DestVT == MVT::f32)  in LowerSINT_TO_FP()
2635   assert(DestVT == MVT::f64);  in LowerSINT_TO_FP()
2816   EVT DestVT = Op.getValueType();  in LowerFP_TO_INT()  local
2819   if (SrcVT == MVT::f16 && DestVT == MVT::i16)  in LowerFP_TO_INT()
2823   if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {  in LowerFP_TO_INT()
2840   if (DestVT == MVT::i64 && (SrcVT == MVT::f32 || SrcVT == MVT::f64))  in LowerFP_TO_INT()
4018     EVT DestVT = N->getValueType(0);  in PerformDAGCombine()  local
4025     if (DestVT.isVector()) {  in PerformDAGCombine()
4029         unsigned NElts = DestVT.getVectorNumElements();  in PerformDAGCombine()
4032           EVT DestEltVT = DestVT.getVectorElementType();  in PerformDAGCombine()
4041           return DAG.getBuildVector(DestVT, SL, CastedElts);  in PerformDAGCombine()
4046     if (DestVT.getSizeInBits() != 64 || !DestVT.isVector())  in PerformDAGCombine()
4060       return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);  in PerformDAGCombine()
4071       return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);  in PerformDAGCombine()