Home
last modified time | relevance | path

Searched refs:CSR_READ_4 (Results 1 – 25 of 61) sorted by relevance

123

/freebsd-13.1/sys/mips/ingenic/
H A Djz4780_clock.c578 *val = CSR_READ_4(sc, addr); in jz4780_clock_read_4()
590 val = CSR_READ_4(sc, addr); in jz4780_clock_modify_4()
686 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ohci_enable()
717 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
722 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ehci_enable()
742 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
746 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
751 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
757 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
800 reg = CSR_READ_4(sc, JZ_USBRDT); in jz4780_otg_enable()
[all …]
H A Djz4780_efuse.c75 #define CSR_READ_4(sc, reg) \ macro
104 while ((CSR_READ_4(sc, JZ_EFUSTATE) & JZ_EFUSE_RD_DONE) == 0) in jz4780_efuse_read_chunk()
111 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
118 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
H A Djz4780_gpio.c110 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
240 val = CSR_READ_4(sc, JZ_GPIO_INT); in jz4780_gpio_pin_probe()
243 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
249 val = CSR_READ_4(sc, JZ_GPIO_PAT0); in jz4780_gpio_pin_probe()
260 val = CSR_READ_4(sc, JZ_GPIO_MASK); in jz4780_gpio_pin_probe()
263 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
269 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
277 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
524 data = CSR_READ_4(sc, JZ_GPIO_PIN); in jz4780_gpio_pin_get()
547 data = CSR_READ_4(sc, JZ_GPIO_PIN); in jz4780_gpio_pin_toggle()
[all …]
/freebsd-13.1/sys/dev/bge/
H A Dif_bge.c627 CSR_READ_4(sc, off); in bge_writembx()
1005 CSR_READ_4(sc, BGE_NVRAM_SWARB); in bge_nvram_getbyte()
1071 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
1122 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
1125 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
2467 dmactl = CSR_READ_4(sc, rdmareg); in bge_blockinit()
4195 val = CSR_READ_4(sc, BGE_MAC_MODE); in bge_reset()
4254 val = CSR_READ_4(sc, 0x7C00); in bge_reset()
5528 mode = CSR_READ_4(sc, BGE_TX_MODE); in bge_init_locked()
5718 if (CSR_READ_4(sc, BGE_MAC_STS) & in bge_ifmedia_sts()
[all …]
/freebsd-13.1/sys/dev/et/
H A Dif_et.c442 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_readreg()
456 val = CSR_READ_4(sc, ET_MII_STAT); in et_miibus_readreg()
487 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_writereg()
542 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); in et_miibus_statchg()
544 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
547 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); in et_miibus_statchg()
591 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
1193 status = CSR_READ_4(sc, ET_INTR_STATUS); in et_intr()
1598 pktfilt = CSR_READ_4(sc, ET_PKTFILT); in et_setmulti()
2277 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); in et_txeof()
[all …]
/freebsd-13.1/sys/dev/dc/
H A Ddcphy.c77 CSR_READ_4(sc, reg) | x)
81 CSR_READ_4(sc, reg) & ~x)
210 mode = CSR_READ_4(dc_sc, DC_NETCFG); in dcphy_service()
265 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_service()
311 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
315 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { in dcphy_status()
368 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in dcphy_status()
372 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in dcphy_status()
H A Dif_dc.c376 CSR_READ_4(sc, DC_BUSCTL); in dc_delay()
524 r = CSR_READ_4(sc, DC_SIO); in dc_eeprom_getword_pnic()
649 val = CSR_READ_4(sc, DC_SIO); in dc_mii_bitbang_read()
693 rval = CSR_READ_4(sc, DC_PN_MII); in dc_miibus_readreg()
709 rval = CSR_READ_4(sc, DC_ROM); in dc_miibus_readreg()
1374 isr = CSR_READ_4(sc, DC_ISR); in dc_netcfg_wait()
2298 reg = CSR_READ_4(sc, DC_AL_PAR0); in dc_attach()
3200 isr = CSR_READ_4(sc, DC_ISR); in dc_tx_underrun()
3253 status = CSR_READ_4(sc, DC_ISR); in dc_poll()
3303 status = CSR_READ_4(sc, DC_ISR); in dc_intr()
[all …]
H A Dpnphy.c211 reg = CSR_READ_4(dc_sc, DC_ISR); in pnphy_status()
214 reg = CSR_READ_4(dc_sc, DC_NETCFG); in pnphy_status()
/freebsd-13.1/sys/dev/alc/
H A Dif_alc.c306 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
333 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
371 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
397 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
492 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
523 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
720 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
747 CSR_READ_4(sc, ALC_WOL_CFG); in alc_get_macaddr_813x()
771 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
808 reg = CSR_READ_4(sc, ALC_SLD); in alc_get_macaddr_816x()
[all …]
/freebsd-13.1/sys/dev/nge/
H A Dif_nge.c250 CSR_READ_4(sc, reg) | (x))
254 CSR_READ_4(sc, reg) & ~(x))
268 CSR_READ_4(sc, NGE_CSR); in nge_delay()
392 val = CSR_READ_4(sc, NGE_MEAR); in nge_mii_bitbang_read()
458 return (CSR_READ_4(sc, reg)); in nge_miibus_readreg()
592 reg = CSR_READ_4(sc, NGE_CFG); in nge_miibus_statchg()
607 reg = CSR_READ_4(sc, NGE_CSR); in nge_miibus_statchg()
645 reg = CSR_READ_4(sc, NGE_CSR); in nge_miibus_statchg()
787 v = CSR_READ_4(sc, NGE_CFG); in nge_reset()
2439 reg = CSR_READ_4(sc, NGE_CSR); in nge_stop_mac()
[all …]
/freebsd-13.1/sys/dev/bfe/
H A Dif_bfe.c891 CSR_READ_4(sc, reg); in bfe_clear_stats()
893 CSR_READ_4(sc, reg); in bfe_clear_stats()
917 CSR_READ_4(sc, BFE_IMASK); in bfe_chip_halt()
1025 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_disable()
1042 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_reset()
1054 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_reset()
1059 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_reset()
1100 val = CSR_READ_4(sc, BFE_RXCONF); in bfe_set_rx_mode()
1261 *val++ = CSR_READ_4(sc, reg); in bfe_stats_update()
1263 *val++ = CSR_READ_4(sc, reg); in bfe_stats_update()
[all …]
/freebsd-13.1/sys/dev/jme/
H A Dif_jme.c361 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_eeprom_read_byte()
386 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
494 par0 = CSR_READ_4(sc, JME_PAR0); in jme_reg_macaddr()
495 par1 = CSR_READ_4(sc, JME_PAR1); in jme_reg_macaddr()
1608 pmcs = CSR_READ_4(sc, JME_PMCS); in jme_setwol()
2719 CSR_READ_4(sc, JME_GHC); in jme_reset()
2735 ghc = CSR_READ_4(sc, JME_GHC); in jme_reset()
2741 CSR_READ_4(sc, JME_GPREG1); in jme_reset()
2748 CSR_READ_4(sc, JME_GHC); in jme_reset()
2886 reg = CSR_READ_4(sc, JME_PMCS); in jme_init_locked()
[all …]
/freebsd-13.1/sys/dev/sis/
H A Dif_sis.c198 CSR_READ_4(sc, reg) | (x))
202 CSR_READ_4(sc, reg) & ~(x))
231 CSR_READ_4(sc, SIS_CSR); in sis_delay()
418 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
448 val = CSR_READ_4(sc, SIS_EECTL); in sis_mii_bitbang_read()
489 if (!CSR_READ_4(sc, NS_BMSR)) in sis_miibus_readreg()
728 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_ns()
767 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_ns()
805 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_sis()
836 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_sis()
[all …]
/freebsd-13.1/sys/dev/bwi/
H A Dbwimac.c200 return CSR_READ_4(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
470 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
476 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
571 val = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_test()
1451 CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_start()
1452 CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_start()
1470 CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_stop()
1500 CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_config_ps()
1565 val = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_get_property()
1577 val = CSR_READ_4(sc, BWI_STATE_HI); in bwi_mac_get_property()
[all …]
H A Dif_bwi.c756 val = CSR_READ_4(sc, BWI_ID_HI); in bwi_regwin_info()
790 info = CSR_READ_4(sc, BWI_INFO); in bwi_bbp_attach()
922 val = CSR_READ_4(sc, BWI_FLAGS); in bwi_bus_init()
1255 CSR_READ_4(sc, BWI_TXSTATUS1); in bwi_init_statechg()
1476 CSR_READ_4(sc, BWI_MAC_INTR_MASK); in bwi_stop_locked()
3523 val = CSR_READ_4(sc, BWI_STATE_LO); in bwi_regwin_is_enabled()
3601 CSR_READ_4(sc, BWI_STATE_LO); in bwi_regwin_disable()
3610 CSR_READ_4(sc, BWI_STATE_LO); in bwi_regwin_disable()
3629 CSR_READ_4(sc, BWI_STATE_LO); in bwi_regwin_enable()
3649 CSR_READ_4(sc, BWI_STATE_LO); in bwi_regwin_enable()
[all …]
H A Dif_bwivar.h77 #define CSR_READ_4(sc, reg) \ macro
88 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
93 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
98 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
/freebsd-13.1/sys/dev/stge/
H A Dif_stge.c1398 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_link_task()
1419 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_tx_error()
1876 CSR_READ_4(sc,STGE_OctetRcvOk); in stge_stats_update()
1882 CSR_READ_4(sc, STGE_OctetXmtdOk); in stge_stats_update()
1887 CSR_READ_4(sc, STGE_LateCollisions) + in stge_stats_update()
1888 CSR_READ_4(sc, STGE_MultiColFrames) + in stge_stats_update()
1889 CSR_READ_4(sc, STGE_SingleColFrames)); in stge_stats_update()
1911 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_reset()
1949 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_reset()
2146 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; in stge_init_locked()
[all …]
/freebsd-13.1/sys/dev/altera/atse/
H A Dif_atse.c182 #define CSR_READ_4(sc, reg) \ macro
407 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
413 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
458 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_rxfilter_locked()
748 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
790 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
828 val4 = CSR_READ_4(sc, TX_CMD_STAT); in atse_reset()
832 val4 = CSR_READ_4(sc, RX_CMD_STAT); in atse_reset()
838 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
856 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
[all …]
/freebsd-13.1/sys/dev/ale/
H A Dif_ale.c218 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
245 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
295 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
368 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
396 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
397 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
1522 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_setwol()
2081 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_mac_config()
2662 CSR_READ_4(sc, ALE_WOL_CFG); in ale_init_locked()
2878 reg = CSR_READ_4(sc, ALE_TXQ_CFG); in ale_stop()
[all …]
/freebsd-13.1/sys/dev/lge/
H A Dif_lge.c200 CSR_READ_4(sc, reg) | (x))
204 CSR_READ_4(sc, reg) & ~(x))
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
236 val = CSR_READ_4(sc, LGE_EEDATA);
301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
424 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
551 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
680 CSR_READ_4(sc, LGE_ISR);
[all …]
/freebsd-13.1/sys/dev/age/
H A Dif_age.c224 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_readreg()
254 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_writereg()
345 reg = CSR_READ_4(sc, AGE_SPI_CTRL); in age_get_macaddr()
374 ea[0] = CSR_READ_4(sc, AGE_PAR0); in age_get_macaddr()
375 ea[1] = CSR_READ_4(sc, AGE_PAR1); in age_get_macaddr()
1428 reg = CSR_READ_4(sc, AGE_MAC_CFG); in age_setwol()
1940 reg = CSR_READ_4(sc, AGE_MAC_CFG); in age_mac_config()
2539 CSR_READ_4(sc, AGE_MASTER_CFG); in age_reset()
2826 reg = CSR_READ_4(sc, AGE_MAC_CFG); in age_init_locked()
2932 reg = CSR_READ_4(sc, AGE_MAC_CFG); in age_stop_txmac()
[all …]
/freebsd-13.1/sys/mips/atheros/ar531x/
H A Dif_are.c462 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) in are_miibus_readreg()
466 return (CSR_READ_4(sc, CSR_MIIDATA) & 0xffff); in are_miibus_readreg()
485 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) in are_miibus_writereg()
551 if ((CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) == 0) in are_reset()
555 if (CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) in are_reset()
834 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7; in are_encap()
893 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7; in are_start_locked()
920 CSR_READ_4(sc, CSR_MACCTL) & ~(MACCTL_TE | MACCTL_RE)); in are_stop()
933 macctl = CSR_READ_4(sc, CSR_MACCTL); in are_set_filter()
1633 status = CSR_READ_4(sc, CSR_STATUS); in are_intr()
[all …]
/freebsd-13.1/sys/dev/vge/
H A Dif_vgevar.h226 #define CSR_READ_4(sc, reg) \ macro
238 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
245 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
/freebsd-13.1/sys/dev/my/
H A Dif_my.c143 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
144 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
180 miir = CSR_READ_4(sc, MY_MANAGEMENT); in my_send_cmd_to_phy()
244 miir = CSR_READ_4(sc, MY_MANAGEMENT); in my_phy_readreg()
332 rxfilt = CSR_READ_4(sc, MY_TCRRCR); in my_setmulti()
719 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { in my_setcfg()
724 if (!(CSR_READ_4(sc, MY_TCRRCR) & in my_setcfg()
756 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) in my_reset()
1206 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { in my_txeof()
1227 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { in my_txeof()
[all …]
/freebsd-13.1/sys/dev/ipw/
H A Dif_ipw.c1258 r = CSR_READ_4(sc, IPW_CSR_RX_READ); in ipw_rx_intr()
1351 r = CSR_READ_4(sc, IPW_CSR_TX_READ); in ipw_tx_intr()
1388 r = CSR_READ_4(sc, IPW_CSR_INTR); in ipw_intr()
1818 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_stop_master()
1834 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_reset()
1846 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_reset()
1851 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_reset()
1993 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_load_firmware()
2003 tmp = CSR_READ_4(sc, IPW_CSR_IO); in ipw_load_firmware()
2383 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); in ipw_init_locked()
[all …]

123