674 	val = CSR_READ_4(sc, BFE_TX_CTRL);  in bfe_miibus_statchg()
680 		flow = CSR_READ_4(sc, BFE_RXCONF);  in bfe_miibus_statchg()
690 		flow = CSR_READ_4(sc, BFE_MAC_FLOW);  in bfe_miibus_statchg()
869 	pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;  in bfe_pci_setup()
871 	val = CSR_READ_4(sc, BFE_SBINTVEC);  in bfe_pci_setup()
875 	val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);  in bfe_pci_setup()
891 		CSR_READ_4(sc, reg);  in bfe_clear_stats()
893 		CSR_READ_4(sc, reg);  in bfe_clear_stats()
917 	CSR_READ_4(sc, BFE_IMASK);  in bfe_chip_halt()
938 	val = CSR_READ_4(sc, BFE_SBTMSLOW) &  in bfe_chip_reset()
946 		if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)  in bfe_chip_reset()
965 	val = CSR_READ_4(sc, BFE_DEVCTRL);  in bfe_chip_reset()
968 	else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {  in bfe_chip_reset()
1013 	if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)  in bfe_core_disable()
1025 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_disable()
1042 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1046 	if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)  in bfe_core_reset()
1048 	val = CSR_READ_4(sc, BFE_SBIMSTATE);  in bfe_core_reset()
1054 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1059 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1100 	val = CSR_READ_4(sc, BFE_RXCONF);  in bfe_set_rx_mode()
1165 		ptr[i/2] = CSR_READ_4(sc, 4096 + i);  in bfe_read_eeprom()
1175 		u_int32_t val = CSR_READ_4(sc, reg);  in bfe_wait_bit()
1205 	*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;  in bfe_readphy()
1261 		*val++ = CSR_READ_4(sc, reg);  in bfe_stats_update()
1263 		*val++ = CSR_READ_4(sc, reg);  in bfe_stats_update()
1347 	chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;  in bfe_txeof()
1392 	status = CSR_READ_4(sc, BFE_DMARX_STAT);  in bfe_rxeof()
1456 	istat = CSR_READ_4(sc, BFE_ISTAT);  in bfe_intr()
1465 	CSR_READ_4(sc, BFE_ISTAT);  in bfe_intr()