| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCFGOptimizer.cpp | 104 MI.getOperand(1).setMBB(NewTarget); in InvertAndChangeJumpTarget()
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| H A D | HexagonInstrInfo.cpp | 623 Loop->getOperand(0).setMBB(TBB); in insertBranch()
665 Loop->getOperand(0).setMBB(TBB); in insertBranch()
4335 MI.getOperand(TargetPos).setMBB(NewTarget); in invertAndChangeJumpTarget()
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| H A D | HexagonHardwareLoops.cpp | 1953 MO.setMBB(NewPH); in createPreheaderForLoop()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 673 void setMBB(MachineBasicBlock *MBB) { in setMBB() function
784 Op.setMBB(MBB);
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFixIrreducibleControlFlow.cpp | 342 Op.setMBB(Map[Op.getMBB()]); in run()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachineBasicBlock.cpp | 803 MO.setMBB(this); in transferSuccessorsAndUpdatePHIs()
985 i->getOperand(ni+1).setMBB(NMBB); in SplitCriticalEdge()
1210 I->getOperand(i).setMBB(New); in ReplaceUsesOfBlockWith()
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| H A D | TailDuplicator.cpp | 515 MI.getOperand(Idx + 1).setMBB(SrcBB); in updateSuccessorsPHIs()
527 MI.getOperand(Idx + 1).setMBB(SrcBB); in updateSuccessorsPHIs()
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| H A D | EarlyIfConversion.cpp | 509 PI.PHI->getOperand(i-1).setMBB(Head); in rewritePHIOperands()
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| H A D | TargetInstrInfo.cpp | 333 MO.setMBB(Pred[j].getMBB()); in PredicateInstruction()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCBranchCoalescing.cpp | 409 MO.setMBB(TargetMBB); in moveAndUpdatePHIs()
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| H A D | PPCReduceCRLogicals.cpp | 75 MO.setMBB(NewMBB); in updatePHIs()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 275 void setMBB(MachineBasicBlock &MBB);
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallLowering.cpp | 345 MIRBuilder.setMBB(MBB); in lowerFormalArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 369 MIRBuilder.setMBB(MBB); in lowerFormalArguments()
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| H A D | X86CondBrFolding.cpp | 197 MO.setMBB(NewMBB); in fixPHIsInSucc()
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| H A D | X86FlagsCopyLowering.cpp | 328 OpMBB.setMBB(&NewMBB); in splitBlock()
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| H A D | X86SpeculativeLoadHardening.cpp | 246 Br->getOperand(0).setMBB(&NewMBB); in splitEdge()
303 OpMBB.setMBB(&NewMBB); in splitEdge()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsConstantIslandPass.cpp | 1605 BMI->getOperand(BMITargetOperand).setMBB(DestBB); in fixupConditionalBr()
1606 MI->getOperand(TargetOperand).setMBB(NewDest); in fixupConditionalBr()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 36 void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) { in setMBB() function in MachineIRBuilder
45 setMBB(*MI.getParent()); in setInstr()
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| H A D | IRTranslator.cpp | 451 MIRBuilder.setMBB(*FalseMBB); in translateSwitch()
1750 EntryBuilder->setMBB(*EntryBB); in runOnMachineFunction()
1824 CurBuilder->setMBB(MBB); in runOnMachineFunction()
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| H A D | RegBankSelect.cpp | 631 MIRBuilder.setMBB(*MBB); in runOnMachineFunction()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 485 MIRBuilder.setMBB(MBB); in lowerFormalArguments()
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| H A D | ARMConstantIslandPass.cpp | 1706 BMI->getOperand(0).setMBB(DestBB); in fixupConditionalBr()
1707 MI->getOperand(0).setMBB(NewDest); in fixupConditionalBr()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMachineCFGStructurizer.cpp | 315 PHI.getOperand(Index * 2 + 2).setMBB(NewPred); in setPhiPred()
1285 UI.setMBB(Succ); in fixMBBTerminator()
1319 UI.setMBB(ExternalSucc); in fixRegionTerminator()
2559 UI.setMBB(EntrySucc); in splitEntry()
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| H A D | AMDILCFGStructurizer.cpp | 560 MI->getOperand(0).setMBB(MBB); in setTrueBranch()
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