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Searched refs:getSubReg (Results 1 – 25 of 121) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
934 if (MODef.getSubReg()) in getNextRewritableSource()
977 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
1054 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1064 return MODef.getSubReg() == 0; in getNextRewritableSource()
1323 if (!MI.getOperand(0).getSubReg() && in isLoadFoldable()
1836 if (DefOp.getSubReg() != DefSubReg) in getNextSourceFromBitcast()
1874 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1923 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
2014 if (Def->getOperand(2).getSubReg()) in getNextSourceFromSubregToReg()
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H A DCalcSpillWeights.cpp57 sub = mi->getOperand(0).getSubReg(); in copyHint()
59 hsub = mi->getOperand(1).getSubReg(); in copyHint()
61 sub = mi->getOperand(1).getSubReg(); in copyHint()
63 hsub = mi->getOperand(0).getSubReg(); in copyHint()
73 unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); in copyHint()
H A DDetectDeadLanes.cpp163 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
202 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
298 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
347 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
399 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
413 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
428 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
461 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
H A DTargetInstrInfo.cpp168 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl()
169 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl()
170 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl()
435 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy()
510 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
549 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) { in foldMemoryOperand()
889 MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
1163 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1189 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1214 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
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H A DTargetRegisterInfo.cpp280 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
319 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
328 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
338 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
339 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
H A DMachineOperand.cpp77 if (SubIdx && getSubReg()) in substVirtReg()
78 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
86 if (getSubReg()) { in substPhysReg()
87 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg()
269 getSubReg() == Other.getSubReg(); in isIdenticalTo()
332 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
766 if (unsigned SubReg = getSubReg()) { in print()
H A DRegAllocFast.cpp711 if (!MO.getSubReg()) { in setPhysReg()
718 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
749 (MO.getSubReg() && MI.readsVirtualRegister(Reg))) { in handleThroughOperands()
786 } else if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) { in handleThroughOperands()
874 CopyDstSub = MI.getOperand(0).getSubReg(); in allocateInstruction()
875 CopySrcSub = MI.getOperand(1).getSubReg(); in allocateInstruction()
907 if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) in allocateInstruction()
H A DOptimizePHIs.cpp120 !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
121 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp261 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
437 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
494 !UseMI->getOperand(1).getSubReg()) { in foldOperand()
496 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
540 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
543 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
634 if (Op.getSubReg() != AMDGPU::NoSubRegister || in getImmOrMaterializedImm()
923 Src0->getSubReg() != Src1->getSubReg() || in isClamp()
924 Src0->getSubReg() != AMDGPU::NoSubRegister) in isClamp()
1067 Src0->getSubReg() == Src1->getSubReg() && in isOMod()
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H A DR600ExpandSpecialInstrs.cpp224 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
225 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
230 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
231 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
239 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DSIShrinkInstructions.cpp307 TRI.getSubRegIndexLaneMask(MO.getSubReg()); in instAccessReg()
332 Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I)); in getSubRegForIndex()
366 unsigned Tsub = MovT.getOperand(0).getSubReg(); in matchSwap()
372 unsigned Xsub = Xop.getSubReg(); in matchSwap()
381 if (YTop.getSubReg() != Tsub) in matchSwap()
387 MovY.getOperand(1).getSubReg() != Tsub) in matchSwap()
391 unsigned Ysub = MovY.getOperand(0).getSubReg(); in matchSwap()
417 I->getOperand(0).getSubReg() != Xsub) { in matchSwap()
H A DSIFrameLowering.cpp67 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitFlatScratchInit()
68 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitFlatScratchInit()
380 unsigned RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
381 unsigned RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
382 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
439 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitEntryFunctionScratchSetup()
440 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchSetup()
446 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
474 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
475 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
H A DSIOptimizeExecMaskingPreRA.cpp148 unsigned CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
152 CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
171 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS); in optimizeVcndVcmpPair()
190 .addReg(CCReg, CC->getSubReg()); in optimizeVcndVcmpPair()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp260 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
322 if (!Op.getSubReg()) in profit()
326 if (MI->getOperand(1).getSubReg() != 0) in profit()
445 if (Op.getSubReg()) in isProfitable()
608 unsigned SR = Op.getSubReg(); in createHalfInstr()
679 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
746 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
774 .addReg(Op1.getReg(), RS, Op1.getSubReg()) in splitExt()
1081 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg()) in replaceSubregUses()
1088 switch (Op.getSubReg()) { in replaceSubregUses()
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H A DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonAsmPrinter.cpp143 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? in PrintAsmOperand()
471 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
472 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
548 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
549 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
560 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
561 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
574 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
575 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
H A DHexagonSplitConst32AndConst64.cpp90 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
91 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
H A DHexagonExpandCondsets.cpp179 Sub(Op.getSubReg()) {} in RegisterRef()
324 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags()
376 unsigned DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange()
593 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
649 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
675 unsigned DR = MD.getReg(), DSR = MD.getSubReg(); in split()
885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
887 PredOp.getSubReg()); in predicateAt()
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H A DRDFCopy.cpp47 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy()
48 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy()
129 return S.getSubReg(); in run()
H A DHexagonInstrInfo.cpp843 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
844 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
1173 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1177 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1200 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1205 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1251 assert(Op1.getSubReg() == 0); in expandPostRAPseudo()
1285 assert(Op1.getSubReg() == 0); in expandPostRAPseudo()
1842 unsigned BaseSubA = BaseA.getSubReg(); in areMemAccessesTriviallyDisjoint()
1850 unsigned BaseSubB = BaseB.getSubReg(); in areMemAccessesTriviallyDisjoint()
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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp440 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
441 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
442 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
443 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
445 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
446 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
447 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
448 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
450 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
451 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp145 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
147 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
149 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
151 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
153 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp187 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
188 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
199 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
200 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp36 MO.getSubReg() == SystemZ::subreg_l32 || in getRC32()
37 MO.getSubReg() == SystemZ::subreg_hl32) in getRC32()
40 MO.getSubReg() == SystemZ::subreg_h32 || in getRC32()
41 MO.getSubReg() == SystemZ::subreg_hh32) in getRC32()
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCRegisterInfo.cpp27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
32 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo

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