| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1018 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 975 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
1016 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger()); in LowerSELECT_CC()
1042 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
1994 LHSCC = ISD::getSetCCInverse(LHSCC, in PerformDAGCombine()
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| H A D | AMDGPUISelLowering.cpp | 3490 ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), in performSelectCombine()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1471 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); in changeVectorFPCCToAArch64CC()
1718 CC = getSetCCInverse(CC, isInteger); in emitConjunctionRec()
2189 CC = ISD::getSetCCInverse(CC, true); in LowerXOR()
4676 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl); in LowerSETCC()
4695 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2); in LowerSETCC()
4756 CC = ISD::getSetCCInverse(CC, true); in LowerSELECT_CC()
4760 CC = ISD::getSetCCInverse(CC, true); in LowerSELECT_CC()
4767 CC = ISD::getSetCCInverse(CC, true); in LowerSELECT_CC()
4775 CC = ISD::getSetCCInverse(CC, true); in LowerSELECT_CC()
4818 CC = ISD::getSetCCInverse(CC, true); in LowerSELECT_CC()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 268 CCCode = getSetCCInverse(CCCode, /*isInteger=*/true); in softenSetCCOperands()
2080 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); in simplifySetCCWithAnd()
2169 NewCond = getSetCCInverse(NewCond, /*isInteger=*/true); in optimizeSetCCOfSignedTruncationCheck()
2360 ISD::CondCode InvCond = ISD::getSetCCInverse( in SimplifySetCC()
2525 CC = ISD::getSetCCInverse(CC, in SimplifySetCC()
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| H A D | LegalizeDAG.cpp | 1639 InvCC = getSetCCInverse(CCCode, OpVT.isInteger()); in LegalizeSetCCCondCode()
3632 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, in ExpandNode()
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| H A D | DAGCombiner.cpp | 6170 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), in visitXOR()
18618 CC = ISD::getSetCCInverse(CC, CmpOpVT.isInteger()); in SimplifySelectCC()
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| H A D | SelectionDAG.cpp | 360 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { in getSetCCInverse() function in ISD
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 711 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
745 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 3572 CC = ISD::getSetCCInverse(CC, true); in getSETCCInGPR()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2423 CC = ISD::getSetCCInverse(CC, !IsFP); in getVectorComparisonOrInvert()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 33874 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), in combineVSelectWithAllOnesOrZeros()
34330 CC = ISD::getSetCCInverse(CC, true); in combineSelect()
34400 CC = ISD::getSetCCInverse(CC, true); in combineSelect()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4480 CC = ISD::getSetCCInverse(CC, true); in LowerSELECT_CC()
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