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Searched refs:getKillRegState (Results 1 – 25 of 60) sorted by relevance

123

/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp155 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
156 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
160 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
161 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
188 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
189 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
196 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLogic()
341 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expand()
610 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expand()
726 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
[all …]
H A DAVRRelaxMemOperations.cpp113 .addReg(Src.getReg(), getKillRegState(Src.isKill())); in relax()
117 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
H A DAVRInstrInfo.cpp54 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
63 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
65 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
156 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DAVRFrameLowering.cpp266 .addReg(Reg, getKillRegState(IsNotLiveIn)) in spillCalleeSavedRegisters()
335 getKillRegState(SrcIsKill)); in fixStackStores()
338 getKillRegState(SrcIsKill)); in fixStackStores()
341 .addReg(SrcReg, getKillRegState(SrcIsKill)); in fixStackStores()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp324 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
332 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
336 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
347 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
364 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
368 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
412 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
415 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
418 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
421 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
63 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
99 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DMLxExpansionPass.cpp294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
295 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
306 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DARMLoadStoreOptimizer.cpp735 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
738 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
748 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
754 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
759 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
801 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
810 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
1312 .addReg(Base, getKillRegState(BaseKill)) in MergeBaseUpdateLSMultiple()
1439 getKillRegState(MO.isKill()))); in MergeBaseUpdateLoadStore()
1677 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp38 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
41 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
136 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
141 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrBuilder.h160 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
168 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
169 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp2073 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
2077 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
2099 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
2100 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
2104 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
2105 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
2123 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_ri()
2127 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_ri()
2146 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rii()
2151 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rii()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
H A DXCoreInstrInfo.cpp341 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
353 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
376 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2385 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
2396 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2480 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2484 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
2505 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2508 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2576 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2582 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2589 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
2595 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
H A DAArch64AdvSIMDScalarPass.cpp279 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
364 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
365 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
H A DAArch64FastISel.cpp432 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
1314 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rr()
1358 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_ri()
1401 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rs()
1402 .addReg(RHSReg, getKillRegState(RHSIsKill)) in emitAddSub_rs()
1446 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rx()
2597 .addReg(TmpReg1, getKillRegState(true)) in selectCmp()
3023 .addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
4185 .addReg(Op0, getKillRegState(Op0IsKill)); in emitLSR_ri()
4306 .addReg(Op0, getKillRegState(Op0IsKill)); in emitASR_ri()
[all …]
H A DAArch64ExpandPseudoInsts.cpp625 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) in expandCMP_SWAP()
642 .addReg(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP()
706 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead())) in expandCMP_SWAP_128()
714 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead())) in expandCMP_SWAP_128()
722 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
735 .addReg(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
H A DAArch64SIMDInstrOpt.cpp432 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement()
434 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement()
440 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill()); in optimizeVectElement()
640 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp90 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
105 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
106 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
131 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
104 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp90 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill()); in splitMove()
294 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)); in emitGRX32Move()
299 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)) in emitGRX32Move()
794 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit)); in copyPhysReg()
815 .addReg(SrcRegHi, getKillRegState(KillSrc)) in copyPhysReg()
816 .addReg(SrcRegLo, getKillRegState(KillSrc)); in copyPhysReg()
831 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1); in copyPhysReg()
847 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
881 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
895 .addReg(SrcReg, getKillRegState(isKill)), in storeRegToStackSlot()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp113 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
140 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
181 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
320 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
745 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
746 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
756 unsigned KillSrc = getKillRegState(Src.isKill()); in expandCvtFPInt()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp496 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
504 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
521 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
529 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
591 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRSpilling()
684 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill())); in lowerCRBitSpilling()
771 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerVRSAVESpilling()
H A DPPCFrameLowering.cpp876 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
922 .addReg(ScratchReg, getKillRegState(true)) in emitPrologue()
930 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
1460 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
1538 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
2092 getKillRegState(true)), in spillCalleeSavedRegisters()
2099 .addReg(Reg, getKillRegState(true)); in spillCalleeSavedRegisters()
2138 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); in restoreCRs()
2142 .addReg(MoveReg, getKillRegState(!CR4Spilled))); in restoreCRs()
2146 .addReg(MoveReg, getKillRegState(true))); in restoreCRs()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp694 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
695 .addReg(cmpOp2, getKillRegState(MO2IsKill)) in runOnMachineFunction()
700 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()

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