394           ResultReg).addReg(ZeroReg, getKillRegState(true));  in materializeInt()
432         .addReg(TmpReg, getKillRegState(true));  in materializeFP()
1314       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rr()
1315       .addReg(RHSReg, getKillRegState(RHSIsKill));  in emitAddSub_rr()
1358       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_ri()
1401       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rs()
1402       .addReg(RHSReg, getKillRegState(RHSIsKill))  in emitAddSub_rs()
1446       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rx()
1447       .addReg(RHSReg, getKillRegState(RHSIsKill))  in emitAddSub_rx()
1505         .addReg(LHSReg, getKillRegState(LHSIsKill));  in emitFCmp()
1516       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitFCmp()
1517       .addReg(RHSReg, getKillRegState(RHSIsKill));  in emitFCmp()
1882         .addReg(ResultReg, getKillRegState(true))  in emitLoad()
2378           .addReg(SrcReg, getKillRegState(SrcIsKill));  in emitCompareAndBranch()
2509       .addReg(ConstrainedCondReg, getKillRegState(CondRegIsKill))  in selectBranch()
2552         .addReg(AArch64::WZR, getKillRegState(true));  in selectCmp()
2592         .addReg(AArch64::WZR, getKillRegState(true))  in selectCmp()
2593         .addReg(AArch64::WZR, getKillRegState(true))  in selectCmp()
2597         .addReg(TmpReg1, getKillRegState(true))  in selectCmp()
2598         .addReg(AArch64::WZR, getKillRegState(true))  in selectCmp()
2611       .addReg(AArch64::WZR, getKillRegState(true))  in selectCmp()
2612       .addReg(AArch64::WZR, getKillRegState(true))  in selectCmp()
2782         .addReg(CondReg, getKillRegState(CondIsKill))  in selectSelect()
3023         .addReg(DstReg, getKillRegState(true));  in fastLowerArguments()
3603       .addReg(SrcReg, getKillRegState(SrcRegIsKill));  in fastLowerIntrinsicCall()
3948         .addReg(SrcReg, getKillRegState(SrcIsKill));  in selectTrunc()
4078           .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSL_ri()
4126         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSL_ri()
4185       .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSR_ri()
4247         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSR_ri()
4306       .addReg(Op0, getKillRegState(Op0IsKill));  in emitASR_ri()
4356         .addReg(Op0, getKillRegState(Op0IsKill))  in emitASR_ri()
4512         .addReg(Reg, getKillRegState(true))  in optimizeIntExtLoad()
4556             .addReg(SrcReg, getKillRegState(SrcIsKill))  in selectIntExt()