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Searched refs:getInstr (Results 1 – 25 of 56) sorted by relevance

123

/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp147 MachineInstr &MI1 = *SU.getInstr(); in apply()
208 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
275 MachineInstr &L0 = *S0.getInstr(); in apply()
288 MachineInstr &L1 = *S1.getInstr(); in apply()
323 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
324 MachineInstr *DstInst = Dst->getInstr(); in adjustSchedDependency()
421 MachineInstr *SrcI = Src->getInstr(); in restoreLatency()
433 MachineInstr *DstI = Dst->getInstr(); in restoreLatency()
479 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
491 MachineInstr &SrcInst = *Src->getInstr(); in isBestZeroLatency()
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H A DHexagonMachineScheduler.cpp75 if (QII.mayBeCurLoad(*SUd->getInstr())) in hasDependence()
78 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
99 if (!SU || !SU->getInstr()) in isResourceAvailable()
104 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
106 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
157 switch (SU->getInstr()->getOpcode()) { in reserveResources()
159 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
180 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
406 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
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H A DHexagonHazardRecognizer.cpp41 MachineInstr *MI = SU->getInstr(); in getHazardType()
104 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
110 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
161 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
162 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp415 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
509 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
510 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
511 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
666 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
1311 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
1312 MachineInstr &I = *SUI->getInstr(); in isLegalToPacketizeTogether()
1313 MachineInstr &J = *SUJ->getInstr(); in isLegalToPacketizeTogether()
1622 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPruneDependencies()
1623 MachineInstr &I = *SUI->getInstr(); in isLegalToPruneDependencies()
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H A DHexagonISelLoweringHVX.cpp475 SDValue HalfV0 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
476 SDValue HalfV1 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
525 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in createHvxPrefixPred()
864 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, in extractHvxSubvectorPred()
988 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in insertHvxSubvectorPred()
1285 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMul()
1309 SDValue T2 = getInstr(Hexagon::V6_vmpyiewuh_acc, dl, ResTy, in LowerHvxMul()
1343 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMulh()
1376 SDValue T1 = getInstr(Hexagon::V6_vmpyiewuh_acc, dl, ResTy, in LowerHvxMulh()
1397 SDValue P = getInstr(Hexagon::V6_lvsplatw, dl, ResTy, in LowerHvxMulh()
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H A DHexagonISelLowering.cpp1960 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG); in LowerVECTOR_SHUFFLE()
1985 return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG); in LowerVECTOR_SHUFFLE()
1987 return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG); in LowerVECTOR_SHUFFLE()
1999 return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG); in LowerVECTOR_SHUFFLE()
2001 return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG); in LowerVECTOR_SHUFFLE()
2058 return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG); in LowerBITCAST()
2121 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, in buildVector32()
2409 return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG); in expandPredicate()
2418 return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG); in contractPredicate()
2470 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG); in LowerBUILD_VECTOR()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMacroFusion.cpp72 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
73 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
141 if (DAG->ExitSU.getInstr()) in apply()
149 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
167 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
H A DScheduleDAGInstrs.cpp263 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
286 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
383 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
421 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
492 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
524 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) { in addChainDependency()
1116 SU.getInstr()->dump(); in dumpNode()
1122 if (EntrySU.getInstr() != nullptr) in dump()
1126 if (ExitSU.getInstr() != nullptr) in dump()
1139 SU->getInstr()->print(oss, /*SkipOpers=*/true); in getGraphNodeLabel()
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H A DSlotIndexes.cpp115 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
128 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
221 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
259 if (itr->getInstr()) { in dump()
260 dbgs() << *itr->getInstr(); in dump()
H A DMachinePipeliner.cpp605 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
663 if (I.getInstr()->isPHI()) { in updatePhiDependences()
1073 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence()) in apply()
1771 SU->getInstr()->dump(); in schedulePipeline()
1862 if (CI->getInstr()->isPHI()) in generatePipelinedLoop()
3148 SU->getInstr()->dump(); in insert()
3161 SU->getInstr()->dump(); in insert()
3423 if (UseSU->getInstr()->isPHI()) in isLoopCarried()
3695 if (SU->getInstr()->isPHI()) in finalizeSchedule()
3701 if (!SU->getInstr()->isPHI()) in finalizeSchedule()
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H A DMachineScheduler.cpp793 MachineInstr *MI = SU->getInstr(); in schedule()
943 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1179 if (EntrySU.getInstr() != nullptr) in dump()
1195 if (ExitSU.getInstr() != nullptr) in dump()
1404 MachineInstr *MI = SU->getInstr(); in scheduleMI()
1842 if (!SU.getInstr()->isCopy()) in apply()
2929 Cand.SU->getInstr(), in initCandidate()
2936 Cand.SU->getInstr(), in initCandidate()
2943 Cand.SU->getInstr(), in initCandidate()
3221 << *SU->getInstr()); in pickNode()
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H A DCriticalAntiDepBreaker.cpp457 MISUnitMap[SU->getInstr()] = SU; in BreakAntiDependencies()
478 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
589 CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp162 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
163 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
196 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
221 MachineInstr *MI = SU->getInstr(); in getAluKind()
295 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
324 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
326 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
395 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
444 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DGCNDPPCombine.cpp196 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
213 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { in createDPPInst()
223 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
238 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
241 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
242 return DPPInst.getInstr(); in createDPPInst()
360 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
H A DSIMachineScheduler.cpp339 RPTracker.setPos(SU->getInstr()); in initRegPressure()
420 TopRPTracker.setPos(SU->getInstr()); in schedule()
1154 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1178 if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr())) in colorExports()
1363 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1392 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1843 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1853 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1874 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
1960 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in schedule()
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H A DGCNIterativeScheduler.cpp53 return SU->getInstr(); in getMachineInstr()
56 return SU.getInstr(); in getMachineInstr()
347 Res.push_back(SU->getInstr()); in detachSchedule()
349 return P.second == SU->getInstr(); in detachSchedule()
H A DGCNSchedStrategy.cpp79 TempTracker.getDownwardPressure(SU->getInstr(), Pressure, MaxPressure); in initCandidate()
83 TempTracker.getUpwardPressure(SU->getInstr(), Pressure, MaxPressure); in initCandidate()
290 << *SU->getInstr()); in pickNode()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp106 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
170 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
205 if (has4RegOps(SU->getInstr())) in dumpSU()
286 LastEmittedMI = SU->getInstr(); in EmitInstruction()
292 LastEmittedMI = SU->getInstr(); in EmitInstruction()
330 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
365 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
H A DSystemZHazardRecognizer.h124 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp38 MachineInstr *MI = SU->getInstr(); in getHazardType()
83 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFixIrreducibleControlFlow.cpp294 unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; in run()
348 MIB.addMBB(MIB.getInstr() in run()
349 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1) in run()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h377 MachineInstr *getInstr() const {
391 ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0);
586 if (SU->isInstr()) return &SU->getInstr()->getDesc();
H A DSlotIndexes.h54 MachineInstr* getInstr() const { return mi; } in getInstr() function
431 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
440 if (I->getInstr())
642 assert(miEntry->getInstr() == &MI &&
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp438 .getInstr(); in loadImmediate()
442 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); in loadImmediate()
450 .getInstr(); in loadImmediate()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp330 MachineInstr *MI = SU->getInstr(); in getHazardType()
388 MachineInstr *MI = SU->getInstr(); in EmitInstruction()

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