| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 330 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
360 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 888 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
898 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
979 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
985 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1013 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1021 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1053 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1079 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
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| H A D | SIISelLowering.cpp | 3777 DAG.getCondCode(CCOpcode)); in lowerICMPIntrinsic()
3806 Src1, DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 896 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
988 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1010 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1632 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1691 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1708 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
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| H A D | LegalizeIntegerTypes.cpp | 3289 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
3345 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
3374 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
3393 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
3410 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
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| H A D | LegalizeDAG.cpp | 1635 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1647 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3555 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3669 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3697 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
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| H A D | TargetLowering.cpp | 274 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
280 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
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| H A D | SelectionDAG.cpp | 1526 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 722 SDValue getCondCode(ISD::CondCode Cond);
945 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
965 False, getCondCode(Cond));
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 843 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonb936c2650111::ARMOperand
2017 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2018 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2044 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
3218 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
5030 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 512 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon7d8c15f70111::AArch64Operand
1575 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
2041 OS << "<condcode " << getCondCode() << ">"; in print()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5546 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC()
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