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Searched refs:getBasePtr (Results 1 – 25 of 44) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp81 SDValue Ptr = N->getBasePtr(); in match()
133 Base = DAG.getTargetLoweringInfo().unwrapAddress(LSBase->getBasePtr()); in match()
H A DLegalizeVectorTypes.cpp301 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()), in ScalarizeVecRes_LOAD()
1305 SDValue Ptr = LD->getBasePtr(); in SplitVecRes_LOAD()
1341 SDValue Ptr = MLD->getBasePtr(); in SplitVecRes_MLOAD()
1408 SDValue Ptr = MGT->getBasePtr(); in SplitVecRes_MGATHER()
1991 SDValue Ptr = MGT->getBasePtr(); in SplitVecOp_MGATHER()
2058 SDValue Ptr = N->getBasePtr(); in SplitVecOp_MSTORE()
2118 SDValue Ptr = N->getBasePtr(); in SplitVecOp_MSCATTER()
2181 SDValue Ptr = N->getBasePtr(); in SplitVecOp_STORE()
4176 SDValue BasePtr = LD->getBasePtr(); in GenWidenVectorLoads()
4326 SDValue BasePtr = LD->getBasePtr(); in GenWidenVectorExtLoads()
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H A DDAGCombiner.cpp12600 Ptr = LD->getBasePtr(); in CombineToPreIndexedLoadStore()
12608 Ptr = ST->getBasePtr(); in CombineToPreIndexedLoadStore()
12825 Ptr = LD->getBasePtr(); in CombineToPostIndexedLoadStore()
12833 Ptr = ST->getBasePtr(); in CombineToPostIndexedLoadStore()
13110 SDValue Ptr = LD->getBasePtr(); in visitLOAD()
13893 SDValue Ptr = St->getBasePtr(); in ShrinkLoadReplaceStoreWithStore()
13959 if (LD->getBasePtr() != Ptr || in ReduceLoadOpStoreWidth()
15082 SDValue Ptr = ST->getBasePtr(); in replaceStoreOfFPConstant()
15427 SDValue Ptr = ST->getBasePtr(); in splitMergedValStore()
18382 LLD->getBasePtr(), RLD->getBasePtr(), in SimplifySelectOps()
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H A DLegalizeTypesGeneric.cpp261 SDValue Ptr = LD->getBasePtr(); in ExpandRes_NormalLoad()
472 SDValue Ptr = St->getBasePtr(); in ExpandOp_NormalStore()
H A DLegalizeFloatTypes.cpp641 L->getChain(), L->getBasePtr(), L->getOffset(), in SoftenFloatRes_LOAD()
653 dl, L->getChain(), L->getBasePtr(), L->getOffset(), in SoftenFloatRes_LOAD()
1028 return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(), in SoftenFloatOp_STORE()
1436 SDValue Ptr = LD->getBasePtr(); in ExpandFloatRes_LOAD()
1720 SDValue Ptr = ST->getBasePtr(); in ExpandFloatOp_STORE()
1866 return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(), in PromoteFloatOp_STORE()
2117 SDLoc(N), L->getChain(), L->getBasePtr(), in PromoteFloatRes_LOAD()
H A DLegalizeIntegerTypes.cpp206 N->getChain(), N->getBasePtr(), in PromoteIntRes_Atomic0()
218 N->getChain(), N->getBasePtr(), in PromoteIntRes_Atomic1()
241 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3), in PromoteIntRes_AtomicCmpSwap()
254 N->getBasePtr(), Op2, Op3, N->getMemOperand()); in PromoteIntRes_AtomicCmpSwap()
542 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
556 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(), in PromoteIntRes_MLOAD()
572 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(), in PromoteIntRes_MGATHER()
1333 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); in PromoteIntOp_STORE()
1364 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask, in PromoteIntOp_MSTORE()
2376 SDValue Ptr = N->getBasePtr(); in ExpandIntRes_LOAD()
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H A DStatepointLowering.cpp842 SI.Bases.push_back(Relocate->getBasePtr()); in LowerStatepoint()
H A DTargetLowering.cpp2413 SDValue Ptr = Lod->getBasePtr(); in SimplifySetCC()
2415 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), in SimplifySetCC()
4743 SDValue BasePTR = LD->getBasePtr(); in scalarizeVectorLoad()
4782 SDValue BasePtr = ST->getBasePtr(); in scalarizeVectorStore()
4856 SDValue Ptr = LD->getBasePtr(); in expandUnalignedLoad()
5011 SDValue Ptr = ST->getBasePtr(); in expandUnalignedStore()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp162 LD->getBasePtr(), LD->getChain()); in selectIndexedLoad()
328 SDValue BasePtr = ST->getBasePtr(); in select()
374 SDValue Ptr = LD->getBasePtr(); in select()
H A DAVRISelLowering.cpp783 Op = LD->getBasePtr().getNode(); in getPreIndexedAddressParts()
791 Op = ST->getBasePtr().getNode(); in getPreIndexedAddressParts()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1334 const SDValue &getBasePtr() const {
1377 const SDValue &getBasePtr() const { return getOperand(1); }
2096 const SDValue &getBasePtr() const { return getOperand(1); }
2127 const SDValue &getBasePtr() const { return getOperand(2); }
2148 const SDValue &getBasePtr() const {
2178 const SDValue &getBasePtr() const { return getOperand(1); }
2214 const SDValue &getBasePtr() const { return getOperand(2); }
2238 const SDValue &getBasePtr() const { return getOperand(3); }
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1154 if (!selectBDVAddr12Only(Load->getBasePtr(), ElemV, Base, Disp, Index) || in tryGather()
1188 if (!selectBDVAddr12Only(Store->getBasePtr(), ElemV, Base, Disp, Index) || in tryScatter()
1232 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() || in isFusableLoadOpStorePattern()
1348 if (!selectBDAddr20Only(StoreNode->getBasePtr(), Base, Disp)) in tryFoldLoadStoreIntoMemOperand()
1403 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode())) in storeLoadCanUseMVC()
1406 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode())) in storeLoadCanUseMVC()
H A DSystemZISelLowering.cpp1821 Load->getBasePtr(), Load->getPointerInfo(), in adjustSubwordCmp()
2901 LoadN->getBasePtr(), LoadN->getMemOperand()); in lowerBITCAST()
3412 Node->getChain(), Node->getBasePtr(), in lowerATOMIC_LOAD()
3421 Node->getBasePtr(), Node->getMemoryVT(), in lowerATOMIC_STORE()
3446 SDValue Addr = Node->getBasePtr(); in lowerATOMIC_LOAD_OP()
3531 Node->getChain(), Node->getBasePtr(), NegSrc2, in lowerATOMIC_LOAD_SUB()
5427 SN->getBasePtr(), SN->getMemoryVT(), in combineSTORE()
5589 LD->getBasePtr() // Ptr in combineBSWAP()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp350 LD->getBasePtr(), LD->getChain())); in tryIndexedLoad()
366 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() }; in tryIndexedBinOp()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp430 SDValue BasePtr = LD->getBasePtr(); in LowerLOAD()
511 SDValue BasePtr = ST->getBasePtr(); in LowerSTORE()
962 N->getChain(), N->getBasePtr(), N->getPointerInfo(), in LowerATOMIC_LOAD()
970 N->getBasePtr(), N->getPointerInfo(), MVT::i16, in LowerATOMIC_LOAD()
976 N->getBasePtr(), N->getPointerInfo(), MVT::i8, in LowerATOMIC_LOAD()
992 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(), in LowerATOMIC_STORE()
1000 N->getBasePtr(), N->getPointerInfo(), MVT::i16, in LowerATOMIC_STORE()
1006 N->getBasePtr(), N->getPointerInfo(), MVT::i8, in LowerATOMIC_STORE()
1801 return DAG.getMemmove(Chain, dl, ST->getBasePtr(), in PerformDAGCombine()
1802 LD->getBasePtr(), in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h1418 const SDValue &getBasePtr() const { return getOperand(2); } in getBasePtr() function
1437 const SDValue &getBasePtr() const { return getOperand(2); } in getBasePtr() function
1506 const SDValue &getBasePtr() const { return getOperand(3); } in getBasePtr() function
H A DX86ISelDAGToDAG.cpp1991 return selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, in selectScalarSSELoad()
2002 return selectAddr(MI, MI->getBasePtr(), Base, Scale, Index, Disp, in selectScalarSSELoad()
2016 return selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, in selectScalarSSELoad()
2033 return selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, in selectScalarSSELoad()
2474 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() || in isFusableLoadOpStorePattern()
2624 if (!selectAddr(LoadNode, LoadNode->getBasePtr(), Base, Scale, Index, Disp, in foldLoadStoreIntoMemOperand()
H A DX86ISelLowering.cpp4265 SDValue Ptr = Ld->getBasePtr(); in MatchingStackOffset()
5703 SDValue Ptr = Load->getBasePtr(); in getTargetConstantFromNode()
7125 SDValue Ptr = LD->getBasePtr(); in LowerAsSplatVectorLoad()
20670 SDValue Ptr = Ld->getBasePtr(); in LowerLoad()
36174 SDValue Base = Ld->getBasePtr(); in getIndexFromUnindexedLoad()
37271 SDValue Ptr = Ld->getBasePtr(); in combineLoad()
37343 Addr = MaskedOp->getBasePtr(); in getParamsForOneTrueMaskedElt()
37851 SDValue Ptr = St->getBasePtr(); in combineStore()
37930 LoAddr = St->getBasePtr(); in combineStore()
41710 return Ld->getBasePtr() == St->getBasePtr(); in IsDesirableToPromoteOp()
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/freebsd-12.1/contrib/llvm/include/llvm/IR/
H A DStatepoint.h397 Value *getBasePtr() const { in getBasePtr() function
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1161 SDValue BasePtr = Store->getBasePtr(); in lowerPrivateTruncStore()
1234 SDValue Ptr = StoreNode->getBasePtr(); in LowerSTORE()
1389 SDValue BasePtr = Load->getBasePtr(); in lowerPrivateExtLoad()
1452 SDValue Ptr = LoadNode->getBasePtr(); in LowerLOAD()
1798 SDValue Ptr = LoadNode->getBasePtr(); in constBufferLoad()
2060 SDValue Ptr = LoadNode->getBasePtr(); in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp69 SDValue Base = LD->getBasePtr(); in SelectIndexedLoad()
466 SDValue Base = ST->getBasePtr(); in SelectIndexedStore()
962 SDValue LDBasePtr = cast<MemSDNode>(SYNode)->getBasePtr(); in isMemOPCandidate()
963 SDValue STBasePtr = cast<MemSDNode>(UUse)->getBasePtr(); in isMemOPCandidate()
2234 SDValue BasePtr = cast<MemSDNode>(N)->getBasePtr(); in rebalanceAddressTrees()
H A DHexagonISelLowering.cpp2588 validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign); in LowerLoad()
2598 SDValue Ptr = SN->getBasePtr(); in LowerStore()
2655 SDValue Base = LN->getBasePtr(); in LowerUnalignedLoad()
3098 std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr()); in shouldReduceLoadWidth()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2737 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(), in LowerF128Load()
2739 EVT addrVT = LdNode->getBasePtr().getValueType(); in LowerF128Load()
2741 LdNode->getBasePtr(), in LowerF128Load()
2806 StNode->getBasePtr(), MachinePointerInfo(), alignment); in LowerF128Store()
2807 EVT addrVT = StNode->getBasePtr().getValueType(); in LowerF128Store()
2809 StNode->getBasePtr(), in LowerF128Store()
2830 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(), in LowerSTORE()
3393 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(), in ReplaceNodeResults()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2453 Ptr = LD->getBasePtr(); in getPreIndexedAddressParts()
2457 Ptr = ST->getBasePtr(); in getPreIndexedAddressParts()
6849 SDValue BasePtr = LD->getBasePtr(); in LowerLOAD()
6874 SDValue BasePtr = ST->getBasePtr(); in LowerSTORE()
7183 RLI.Ptr = LD->getBasePtr(); in canReuseLoadAddress()
9293 SDValue BasePtr = LN->getBasePtr(); in LowerVectorLoad()
9381 SDValue BasePtr = SN->getBasePtr(); in LowerVectorStore()
11114 SDValue Loc = LS->getBasePtr(); in isConsecutiveLS()
12477 Base = LD->getBasePtr(); in expandVSXLoadForLE()
12546 Base = ST->getBasePtr(); in expandVSXStoreForLE()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2806 ST->getBasePtr(), ST->getMemOperand()); in LowerTruncateVectorStore()
3503 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) in addTokenForArgument()
8141 const SDValue &Base = Mem->getBasePtr(); in shouldReduceLoadWidth()
10105 SDValue BasePtr = St.getBasePtr(); in splitStoreSplat()
10178 if (DAG.isBaseWithConstantOffset(St.getBasePtr())) { in replaceZeroVectorStore()
10179 int64_t Offset = St.getBasePtr()->getConstantOperandVal(1); in replaceZeroVectorStore()
10324 SDValue BasePtr = S->getBasePtr(); in splitStores()
11350 Ptr = LD->getBasePtr(); in getPreIndexedAddressParts()
11353 Ptr = ST->getBasePtr(); in getPreIndexedAddressParts()
11371 Ptr = LD->getBasePtr(); in getPostIndexedAddressParts()
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