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Searched refs:constrainRegClass (Results 1 – 25 of 33) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp374 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
377 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass); in AssignSlot()
380 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass); in AssignSlot()
383 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass); in AssignSlot()
H A DSILowerI1Copies.cpp452 MRI->constrainRegClass(Reg, &AMDGPU::SReg_64_XEXECRegClass); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp70 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, in constrainRegClass() function
86 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() function in MachineRegisterInfo
89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
110 if (!::constrainRegClass( in constrainRegAttrs()
H A DTargetInstrInfo.cpp807 MRI.constrainRegClass(RegA, RC); in reassociateOps()
809 MRI.constrainRegClass(RegB, RC); in reassociateOps()
811 MRI.constrainRegClass(RegX, RC); in reassociateOps()
813 MRI.constrainRegClass(RegY, RC); in reassociateOps()
815 MRI.constrainRegClass(RegC, RC); in reassociateOps()
H A DOptimizePHIs.cpp182 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
H A DUnreachableBlockElim.cpp210 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
H A DTailDuplicator.cpp242 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in tailDuplicateAndUpdate()
419 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC); in duplicateInstruction()
H A DTwoAddressInstructionPass.cpp1487 MRI->constrainRegClass(DstReg, RC); in collectTiedOperands()
1602 MRI->constrainRegClass(RegA, RC); in processTiedPairs()
H A DMachineLICM.cpp1398 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) { in EliminateCSE()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp663 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
664 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
1077 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
4013 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
4015 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
4017 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
4019 MRI.constrainRegClass(SrcReg2, RC); in genFusedMultiply()
4079 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
4081 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
4083 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
[all …]
H A DAArch64ConditionalCompares.cpp644 MRI->constrainRegClass(HeadCond[2].getReg(), in convert()
691 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
694 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
H A DAArch64RegisterInfo.cpp414 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp165 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
206 MRI->constrainRegClass(DestReg, in loadRegFromStackSlot()
H A DA15SDOptimizer.cpp643 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
H A DARMBaseRegisterInfo.cpp628 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
H A DARMLoadStoreOptimizer.cpp2291 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2292 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp237 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()
H A DPPCRegisterInfo.cpp1119 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
1145 MRI.constrainRegClass(BaseReg, in resolveFrameIndex()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp612 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass); in insertSelect()
1004 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass); in convertToThreeAddress()
1005 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass); in convertToThreeAddress()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp339 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
475 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
H A DFastISel.cpp2019 if (!MRI.constrainRegClass(Op, RegClass)) { in constrainOperandRegClass()
2227 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in fastEmitInst_extractsubreg()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBankInfo.cpp134 return MRI.constrainRegClass(Reg, &RC); in constrainGenericRegister()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h687 const TargetRegisterClass *constrainRegClass(unsigned Reg,
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp510 if (!MRI.constrainRegClass(DestReg, PreviousClass)) in optimizeSelect()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp966 MRI->constrainRegClass(Reg, &X86::GR32_ABCDRegClass); in rewriteSetCarryExtended()

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