Lines Matching refs:constrainRegClass
578 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
584 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
624 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
628 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
632 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
635 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
663 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
664 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
1077 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
2668 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
2678 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
2799 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
2809 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
2982 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
2987 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
4013 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
4015 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
4017 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
4019 MRI.constrainRegClass(SrcReg2, RC); in genFusedMultiply()
4079 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
4081 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
4083 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
4085 MRI.constrainRegClass(VR, RC); in genMaddR()