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Searched refs:addUse (Results 1 – 22 of 22) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp341 .addUse(SrcReg); in selectFP16CopyFromGPR32()
416 .addUse(SrcReg) in selectCopy()
633 .addUse(LHS) in selectCompareBranch()
663 .addUse(ArgsAddrReg) in selectVaStartDarwin()
664 .addUse(ListReg) in selectVaStartDarwin()
897 .addUse(DefGPRReg); in select()
1273 .addUse(SrcReg) in select()
1310 .addUse(SrcReg) in select()
1391 .addUse(CondReg) in select()
1704 .addUse(DstVec) in selectBuildVector()
[all …]
H A DAArch64SpeculationHardening.cpp233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
371 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
377 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
394 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
401 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
406 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
454 .addUse(Reg); in makeGPRSpeculationSafe()
578 .addUse(SrcReg, RegState::Kill) in expandSpeculationSafeValue()
[all …]
H A DAArch64ExpandPseudoInsts.cpp710 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
711 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
718 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
719 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
722 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
H A DAArch64CallLowering.cpp151 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
H A DAArch64FastISel.cpp5077 .addUse(AddrReg) in selectAtomicCmpXchg()
5078 .addUse(DesiredReg) in selectAtomicCmpXchg()
5079 .addUse(NewReg); in selectAtomicCmpXchg()
5083 .addUse(ResultReg1) in selectAtomicCmpXchg()
5084 .addUse(DesiredReg) in selectAtomicCmpXchg()
5089 .addUse(AArch64::WZR) in selectAtomicCmpXchg()
5090 .addUse(AArch64::WZR) in selectAtomicCmpXchg()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp196 .addUse(Op0) in buildGEP()
197 .addUse(Op1); in buildGEP()
225 .addUse(Op0) in buildPtrMask()
308 .addUse(Addr) in buildLoadInstr()
318 .addUse(Val) in buildStore()
319 .addUse(Addr) in buildStore()
424 .addUse(Src) in buildExtract()
541 .addUse(Src) in buildInsert()
542 .addUse(Op) in buildInsert()
624 .addUse(Addr) in buildAtomicCmpXchgWithSuccess()
[all …]
H A DIRTranslator.cpp323 auto FBinOp = MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1); in translateBinaryOp()
338 .addUse(getOrCreateVReg(*U.getOperand(1))); in translateFSub()
347 .addUse(getOrCreateVReg(*U.getOperand(1))); in translateFNeg()
785 .addUse(getOrCreateVReg(*CI.getOperand(0))) in translateOverflowIntrinsic()
852 .addUse(getOrCreateVReg(*Ptr)) in translateKnownIntrinsic()
1169 MIB.addUse(packRegs(*Arg, MIRBuilder)); in translateCall()
1380 .addUse(getOrCreateVReg(*U.getOperand(0))) in translateVAArg()
1450 .addUse(getOrCreateVReg(*U.getOperand(0))) in translateShuffleVector()
1451 .addUse(getOrCreateVReg(*U.getOperand(1))) in translateShuffleVector()
1452 .addUse(getOrCreateVReg(*U.getOperand(2))); in translateShuffleVector()
[all …]
H A DLegalizerHelper.cpp982 .addUse(MI.getOperand(1).getReg()) in lower()
983 .addUse(MI.getOperand(2).getReg()); in lower()
1010 .addUse(LHS) in lower()
1011 .addUse(RHS); in lower()
1024 .addUse(Res) in lower()
1025 .addUse(ShiftAmt); in lower()
1062 .addUse(Zero->getOperand(0).getReg()) in lower()
1063 .addUse(MI.getOperand(1).getReg()); in lower()
1077 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS); in lower()
1080 .addUse(LHS) in lower()
[all …]
H A DRegBankSelect.cpp163 MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src); in repairReg()
/freebsd-12.1/contrib/llvm/lib/IR/
H A DUse.cpp28 Val->addUse(*this); in swap()
35 RHS.Val->addUse(RHS); in swap()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp168 .addUse(HILOReg); in select()
195 .addUse(LUiReg) in select()
221 .addUse(LUiReg) in select()
303 MIB.addUse(Instruction.RHS); in select()
H A DMipsCallLowering.cpp219 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp529 .addUse(LHSReg) in insertComparison()
530 .addUse(RHSReg) in insertComparison()
547 .addUse(PrevRes) in insertComparison()
688 .addUse(CondReg) in selectSelect()
704 .addUse(TrueReg) in selectSelect()
705 .addUse(FalseReg) in selectSelect()
777 .addUse(AndResult) in select()
827 .addUse(SrcReg) in select()
H A DARMCallLowering.cpp124 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h138 MIB.addUse(Reg); in addSrcToMIB()
141 MIB.addUse(SrcMIB->getOperand(0).getReg()); in addSrcToMIB()
H A DInstructionSelectorImpl.h745 OutMIs[InsnID].addUse(RegNum, RegState::Implicit); in executeMatchTable()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86CallLowering.cpp126 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
436 MIB.addUse(X86::AL, RegState::Implicit); in lowerCall()
H A DX86InstructionSelector.cpp538 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
/freebsd-12.1/contrib/llvm/include/llvm/IR/
H A DValue.h437 void addUse(Use &U) { U.addToList(&UseList); } in addUse() function
674 if (V) V->addUse(*this); in set()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp373 B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1046 void addUse(SDUse &U) { U.addToList(&UseList); }
1184 if (V.getNode()) V.getNode()->addUse(*this);
1189 V.getNode()->addUse(*this);
1195 if (N) N->addUse(*this);
H A DMachineInstrBuilder.h110 const MachineInstrBuilder &addUse(unsigned RegNo, unsigned Flags = 0,