323   auto FBinOp = MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);  in translateBinaryOp()
338         .addUse(getOrCreateVReg(*U.getOperand(1)));  in translateFSub()
347       .addUse(getOrCreateVReg(*U.getOperand(1)));  in translateFNeg()
641   MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);  in translateCast()
785       .addUse(getOrCreateVReg(*CI.getOperand(0)))  in translateOverflowIntrinsic()
786       .addUse(getOrCreateVReg(*CI.getOperand(1)));  in translateOverflowIntrinsic()
852         .addUse(getOrCreateVReg(*Ptr))  in translateKnownIntrinsic()
895         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))  in translateKnownIntrinsic()
896         .addUse(getOrCreateVReg(*CI.getArgOperand(1)));  in translateKnownIntrinsic()
903         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
910         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
917         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
924         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
931         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
938         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
945         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
950         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
955         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))  in translateKnownIntrinsic()
956         .addUse(getOrCreateVReg(*CI.getArgOperand(1)))  in translateKnownIntrinsic()
957         .addUse(getOrCreateVReg(*CI.getArgOperand(2)));  in translateKnownIntrinsic()
1037         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
1043         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
1057         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));  in translateKnownIntrinsic()
1169     MIB.addUse(packRegs(*Arg, MIRBuilder));  in translateCall()
1380     .addUse(getOrCreateVReg(*U.getOperand(0)))  in translateVAArg()
1450       .addUse(getOrCreateVReg(*U.getOperand(0)))  in translateShuffleVector()
1451       .addUse(getOrCreateVReg(*U.getOperand(1)))  in translateShuffleVector()
1452       .addUse(getOrCreateVReg(*U.getOperand(2)));  in translateShuffleVector()
1595           MIB.addUse(ValRegs[j]);  in finishPendingPhis()