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Searched refs:WriteRes (Results 1 – 25 of 34) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td70 def : WriteRes<WriteImm, []> { let Unsupported = 1; }
71 def : WriteRes<WriteI, []> { let Unsupported = 1; }
72 def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
73 def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
74 def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
75 def : WriteRes<WriteIS, []> { let Unsupported = 1; }
76 def : WriteRes<WriteID32, []> { let Unsupported = 1; }
77 def : WriteRes<WriteID64, []> { let Unsupported = 1; }
78 def : WriteRes<WriteIM32, []> { let Unsupported = 1; }
79 def : WriteRes<WriteIM64, []> { let Unsupported = 1; }
[all …]
H A DAArch64SchedKryo.td67 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
69 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
71 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
74 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
76 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
88 def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]>
94 def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]>
96 def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]>
102 def : WriteRes<WriteSys, []> { let Latency = 1; }
103 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
[all …]
H A DAArch64SchedThunderX.td59 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
64 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
70 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
75 def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
86 def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
126 def : WriteRes<WriteVST, [THXT8XUnitLdSt]>;
142 def : WriteRes<WriteBr, [THXT8XUnitBr]>;
144 def : WriteRes<WriteBrReg, [THXT8XUnitBr]>;
147 def : WriteRes<WriteSys, [THXT8XUnitBr]>;
148 def : WriteRes<WriteBarrier, [THXT8XUnitBr]>;
[all …]
H A DAArch64SchedA53.td59 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
60 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
63 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
83 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
97 def : WriteRes<WriteAdr, []> { let Latency = 0; }
114 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
117 def : WriteRes<WriteBr, [A53UnitB]>;
118 def : WriteRes<WriteBrReg, [A53UnitB]>;
119 def : WriteRes<WriteSys, [A53UnitB]>;
120 def : WriteRes<WriteBarrier, [A53UnitB]>;
[all …]
H A DAArch64SchedCyclone.td132 def : WriteRes<WriteImm, [CyUnitI]>;
151 def : WriteRes<WriteI, [CyUnitI]>;
157 def : WriteRes<WriteISReg, [CyUnitIS]> {
165 def : WriteRes<WriteIEReg, [CyUnitIS]> {
172 def : WriteRes<WriteIS, [CyUnitIS]>;
193 def : WriteRes<WriteIM32, [CyUnitIM]> {
197 def : WriteRes<WriteIM64, [CyUnitIM]> {
225 def : WriteRes<WriteLD, [CyUnitLS]> {
235 def : WriteRes<WriteST, [CyUnitLS]> {
266 def : WriteRes<WriteAdr, [CyUnitI]>;
[all …]
H A DAArch64SchedExynosM1.td146 def : WriteRes<WriteID32, [M1UnitC,
149 def : WriteRes<WriteID64, [M1UnitC,
153 def : WriteRes<WriteIM32, [M1UnitC]> { let Latency = 3; }
154 def : WriteRes<WriteIM64, [M1UnitC]> { let Latency = 4;
158 def : WriteRes<WriteExtr, [M1UnitALU,
163 def : WriteRes<WriteAdr, []> { let Latency = 1;
195 def : WriteRes<WriteVST, [M1UnitS,
200 def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
204 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
205 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedExynosM3.td196 def : WriteRes<WriteID32, [M3UnitC,
199 def : WriteRes<WriteID64, [M3UnitC,
202 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
203 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
215 def : WriteRes<WriteLDHi, []> { let Latency = 4;
241 def : WriteRes<WriteVST, [M3UnitS,
246 def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; }
249 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
250 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
251 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedThunderX2T99.td58 // created will be used by a WriteRes later on.
376 def : WriteRes<WriteBr, [THX2T99I2]> {
384 def : WriteRes<WriteBrReg, [THX2T99I2]> {
393 def : WriteRes<WriteAtomic, []> {
501 def : WriteRes<WriteID32, [THX2T99I1]> {
613 def : WriteRes<WriteLDHi, []> {
1109 def : WriteRes<WriteFDiv, [THX2T99F01]> {
1162 def : WriteRes<WriteFMul, [THX2T99F01]> {
1198 def : WriteRes<WriteFCvt, [THX2T99F01]> {
1205 def : WriteRes<WriteFImm, [THX2T99F01]> {
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td66 def : WriteRes<SchedRW, ExePorts> {
83 def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
88 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
89 def : WriteRes<WriteZero, []>;
135 def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
151 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
444 def : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> {
463 def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> {
474 def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
475 def : WriteRes<WriteNop, []>;
[all …]
H A DX86ScheduleAtom.td62 def : WriteRes<SchedRW, RRPorts> {
69 def : WriteRes<SchedRW.Folded, RMPorts> {
76 def : WriteRes<WriteRMW, [AtomPort0]>;
118 def : WriteRes<WriteSETCC, [AtomPort01]>;
135 def : WriteRes<WriteLEA, [AtomPort1]>;
167 def : WriteRes<WriteLoad, [AtomPort0]>;
168 def : WriteRes<WriteStore, [AtomPort0]>;
169 def : WriteRes<WriteStoreNT, [AtomPort0]>;
170 def : WriteRes<WriteMove, [AtomPort01]>;
180 def : WriteRes<WriteZero, []>;
[all …]
H A DX86SchedSandyBridge.td90 def : WriteRes<SchedRW, ExePorts> {
107 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
112 def : WriteRes<WriteMove, [SBPort015]>;
113 def : WriteRes<WriteZero, []>;
181 def : WriteRes<WriteLEA, [SBPort01]>;
463 def : WriteRes<WritePCmpIStrM, [SBPort0]> {
475 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
485 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
524 def : WriteRes<WriteAESIMC, [SBPort5]> {
545 def : WriteRes<WriteCLMul, [SBPort015]> {
[all …]
H A DX86ScheduleBtVer2.td122 def : WriteRes<SchedRW, ExePorts> {
142 def : WriteRes<SchedRW, ExePorts> {
162 def : WriteRes<SchedRW, ExePorts> {
222 def : WriteRes<WriteLAHFSAHF, [JALU01]>;
232 def : WriteRes<WriteLEA, [JALU01]>;
266 def : WriteRes<WriteStore, [JSAGU]>;
267 def : WriteRes<WriteStoreNT, [JSAGU]>;
268 def : WriteRes<WriteMove, [JALU01]>;
273 def : WriteRes<WriteSTMXCSR, [JSAGU]>;
283 def : WriteRes<WriteZero, []>;
[all …]
H A DX86SchedHaswell.td100 def : WriteRes<SchedRW, ExePorts> {
117 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
125 def : WriteRes<WriteZero, []>;
169 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
186 def : WriteRes<WriteLEA, [HWPort15]>;
458 def : WriteRes<WriteVecInsert, [HWPort5]> {
481 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
505 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
535 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
546 def : WriteRes<WriteAESIMC, [HWPort5]> {
[all …]
H A DX86SchedSkylakeClient.td94 def : WriteRes<SchedRW, ExePorts> {
111 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
129 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
162 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
208 def : WriteRes<WriteZero, []>;
407 def : WriteRes<WriteVecInsert, [SKLPort5]> {
472 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
496 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
560 def : WriteRes<WriteCLMul, [SKLPort5]> {
584 def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
[all …]
H A DX86SchedBroadwell.td95 def : WriteRes<SchedRW, ExePorts> {
112 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
165 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
211 def : WriteRes<WriteZero, []>;
417 def : WriteRes<WriteVecInsert, [BWPort5]> {
427 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
481 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
505 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
584 def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
[all …]
H A DX86SchedSkylakeServer.td94 def : WriteRes<SchedRW, ExePorts> {
111 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
163 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
208 def : WriteRes<WriteZero, []>;
408 def : WriteRes<WriteVecInsert, [SKXPort5]> {
473 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
497 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
561 def : WriteRes<WriteCLMul, [SKXPort5]> {
585 def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
[all …]
H A DX86ScheduleZnver1.td136 def : WriteRes<SchedRW, ExePorts> {
157 def : WriteRes<SchedRW, ExePorts> {
174 def : WriteRes<WriteRMW, [ZnAGU]>;
176 def : WriteRes<WriteStore, [ZnAGU]>;
177 def : WriteRes<WriteStoreNT, [ZnAGU]>;
178 def : WriteRes<WriteMove, [ZnALU]>;
181 def : WriteRes<WriteZero, []>;
182 def : WriteRes<WriteLEA, [ZnALU]>;
218 def : WriteRes<WriteSETCC, [ZnALU]>;
474 def : WriteRes<WriteFence, [ZnAGU]>;
[all …]
H A DX86ScheduleBdVer2.td194 def : WriteRes<SchedRW, ExePorts> {
255 def : WriteRes<WriteRMW, [PdStore]>;
261 def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; }
262 def : WriteRes<WriteStore, [PdStore]>;
263 def : WriteRes<WriteStoreNT, [PdStore]>;
264 def : WriteRes<WriteMove, [PdEX01]>;
279 def : WriteRes<WriteZero, [/*No ExePorts*/]>;
294 def : WriteRes<WriteFence, [PdStore]>;
310 def : WriteRes<WriteNop, [PdEX01]>;
458 def : WriteRes<WriteSETCC, [PdEX01]>; // Setcc.
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td65 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
68 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
69 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleR52.td75 def : WriteRes<WriteDIV, [R52UnitDiv]> {
80 def : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; }
109 def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
114 def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
123 def : WriteRes<WriteVST1, []>;
124 def : WriteRes<WriteVST2, []>;
125 def : WriteRes<WriteVST3, []>;
126 def : WriteRes<WriteVST4, []>;
720 def : WriteRes<WriteVLD2, [R52UnitLd]> {
726 def : WriteRes<WriteVLD3, [R52UnitLd]> {
[all …]
H A DARMScheduleSwift.td133 def : WriteRes<WriteALU, [SwiftUnitP01]>;
149 def : WriteRes<WriteCMP, [SwiftUnitP01]>;
290 // Aliasing sub-target specific WriteRes to generic ones
1077 def : WriteRes<WriteVLD1, []>;
1078 def : WriteRes<WriteVLD2, []>;
1079 def : WriteRes<WriteVLD3, []>;
1080 def : WriteRes<WriteVLD4, []>;
1081 def : WriteRes<WriteVST1, []>;
1082 def : WriteRes<WriteVST2, []>;
1083 def : WriteRes<WriteVST3, []>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ13.td38 def : WriteRes<NormalGr, []>;
42 def : WriteRes<Cracked, []> {
46 def : WriteRes<GroupAlone, []> {
51 def : WriteRes<GroupAlone2, []> {
56 def : WriteRes<GroupAlone3, []> {
87 def : WriteRes<FXa, [Z13_FXaUnit]>;
88 def : WriteRes<FXb, [Z13_FXbUnit]>;
89 def : WriteRes<LSU, [Z13_LSUnit]>;
90 def : WriteRes<VecBF, [Z13_VecUnit]>;
91 def : WriteRes<VecDF, [Z13_VecUnit]>;
[all …]
H A DSystemZScheduleZ14.td38 def : WriteRes<NormalGr, []>;
42 def : WriteRes<Cracked, []> {
46 def : WriteRes<GroupAlone, []> {
51 def : WriteRes<GroupAlone2, []> {
56 def : WriteRes<GroupAlone3, []> {
87 def : WriteRes<FXa, [Z14_FXaUnit]>;
88 def : WriteRes<FXb, [Z14_FXbUnit]>;
89 def : WriteRes<LSU, [Z14_LSUnit]>;
90 def : WriteRes<VecBF, [Z14_VecUnit]>;
91 def : WriteRes<VecDF, [Z14_VecUnit]>;
[all …]
H A DSystemZScheduleZEC12.td38 def : WriteRes<NormalGr, []>;
39 def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }
40 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
42 def : WriteRes<GroupAlone, []> {
47 def : WriteRes<GroupAlone2, []> {
52 def : WriteRes<GroupAlone3, []> {
83 def : WriteRes<FXU, [ZEC12_FXUnit]>;
84 def : WriteRes<LSU, [ZEC12_LSUnit]>;
85 def : WriteRes<FPU, [ZEC12_FPUnit]>;
86 def : WriteRes<DFU, [ZEC12_DFUnit]>;
[all …]
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1064 Record *WriteRes = in GenSchedClassTables() local
1068 if (WriteRes->getValueAsBit("Unsupported")) { in GenSchedClassTables()
1072 WLEntry.Cycles += WriteRes->getValueAsInt("Latency"); in GenSchedClassTables()
1073 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps"); in GenSchedClassTables()
1074 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup"); in GenSchedClassTables()
1075 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); in GenSchedClassTables()
1076 SCDesc.BeginGroup |= WriteRes->getValueAsBit("SingleIssue"); in GenSchedClassTables()
1077 SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue"); in GenSchedClassTables()
1080 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); in GenSchedClassTables()
1082 WriteRes->getValueAsListOfInts("ResourceCycles"); in GenSchedClassTables()
[all …]

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