Lines Matching refs:WriteRes

38   def : WriteRes<NormalGr, []>;
39   def : WriteRes<BeginGroup, []> { let BeginGroup  = 1; }
40   def : WriteRes<EndGroup, []>   { let EndGroup    = 1; }
42 def : WriteRes<GroupAlone, []> {
47 def : WriteRes<GroupAlone2, []> {
52 def : WriteRes<GroupAlone3, []> {
65 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
69     def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
83   def : WriteRes<FXU, [ZEC12_FXUnit]>;
84   def : WriteRes<LSU, [ZEC12_LSUnit]>;
85   def : WriteRes<FPU, [ZEC12_FPUnit]>;
86   def : WriteRes<DFU, [ZEC12_DFUnit]>;
88     def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
89     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
90     def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
91     def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
94   def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
97 def : WriteRes<MCD, [ZEC12_MCD]> { let NumMicroOps = 3;