Lines Matching refs:WriteRes

38   def : WriteRes<NormalGr, []>;
39   def : WriteRes<BeginGroup, []> { let BeginGroup  = 1; }
40   def : WriteRes<EndGroup, []>   { let EndGroup    = 1; }
42 def : WriteRes<Cracked, []> {
46 def : WriteRes<GroupAlone, []> {
51 def : WriteRes<GroupAlone2, []> {
56 def : WriteRes<GroupAlone3, []> {
69 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
73     def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
87   def : WriteRes<FXa, [Z13_FXaUnit]>;
88   def : WriteRes<FXb, [Z13_FXbUnit]>;
89   def : WriteRes<LSU, [Z13_LSUnit]>;
90   def : WriteRes<VecBF,  [Z13_VecUnit]>;
91   def : WriteRes<VecDF,  [Z13_VecUnit]>;
92   def : WriteRes<VecDFX, [Z13_VecUnit]>;
93   def : WriteRes<VecMul,  [Z13_VecUnit]>;
94   def : WriteRes<VecStr,  [Z13_VecUnit]>;
95   def : WriteRes<VecXsPm, [Z13_VecUnit]>;
97     def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
98     def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
99     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
100     def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
101     def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
102     def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
103     def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
104     def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
105     def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
108   def : WriteRes<VecFPd,  [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
110   def : WriteRes<VBU,     [Z13_VBUnit]>; // Virtual Branching Unit
113 def : WriteRes<MCD, [Z13_MCD]> { let NumMicroOps = 3;