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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 27) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp406 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
407 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
408 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
409 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
410 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
411 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
413 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
414 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
415 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
430 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
[all …]
H A DARMISelLowering.cpp176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
715 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in ARMTargetLowering()
8044 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
12824 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h367 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1455 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1498 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp144 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
147 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in WebAssemblyTargetLowering()
148 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in WebAssemblyTargetLowering()
904 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp70 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
71 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
113 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
165 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
H A DHexagonISelLowering.cpp1433 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE in HexagonTargetLowering()
1509 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1510 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1511 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
2767 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAG.cpp898 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp278 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DSelectionDAG.cpp614 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
1694 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
2182 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2356 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
3333 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
5310 case ISD::VECTOR_SHUFFLE: in getNode()
H A DDAGCombiner.cpp1586 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
3937 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { in hoistLogicOpWithSameOpcodeHands()
10273 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
15800 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
15834 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
16128 !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) in createBuildVecShuffle()
16287 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT)) in reduceBuildVecToShuffle()
17715 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { in visitVECTOR_SHUFFLE()
17766 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
17767 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && in visitVECTOR_SHUFFLE()
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H A DLegalizeVectorTypes.cpp66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
748 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
2402 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
H A DLegalizeDAG.cpp2911 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
4284 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
H A DTargetLowering.cpp566 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedBits()
1718 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedVectorElts()
H A DLegalizeIntegerTypes.cpp96 case ISD::VECTOR_SHUFFLE: in PromoteIntegerResult()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1506 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp572 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
573 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
641 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
741 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal); in PPCTargetLowering()
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal); in PPCTargetLowering()
901 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom); in PPCTargetLowering()
950 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom); in PPCTargetLowering()
991 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom); in PPCTargetLowering()
9657 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1854 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in X86TargetLowering()
6491 case ISD::VECTOR_SHUFFLE: { in getFauxShuffleMask()
24257 case ISD::VECTOR_SHUFFLE: { in IsSplatVector()
32056 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in isAddSubOrSubAdd()
32109 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in combineShuffleToFMAddSub()
32295 N->getOpcode() == ISD::VECTOR_SHUFFLE && in combineShuffle()
32396 N->getOpcode() == ISD::VECTOR_SHUFFLE && in combineShuffle()
37994 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in isHorizontalBinOp()
37995 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) in isHorizontalBinOp()
38010 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { in isHorizontalBinOp()
[all …]
H A DX86InstrFragmentsSIMD.td283 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp319 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
4087 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
4874 case ISD::VECTOR_SHUFFLE: in LowerOperation()
5131 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp345 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
464 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td533 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp296 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
297 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
298 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
299 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
H A DAMDGPUISelLowering.cpp434 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
470 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand); in NVPTXTargetLowering()

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