| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 183 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding() argument
193 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
197 Forwardings[FirstUseIdx + UseIdx]; in hasPipelineForwarding()
204 unsigned UseClass, unsigned UseIdx) const { in getOperandLatency() argument
212 int UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
218 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| H A D | MCSubtargetInfo.h | 137 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles() argument
144 if (I->UseIdx < UseIdx) in getReadAdvanceCycles()
146 if (I->UseIdx > UseIdx) in getReadAdvanceCycles()
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| H A D | MCSchedule.h | 96 unsigned UseIdx; member
101 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | LiveRangeEdit.cpp | 109 SlotIndex UseIdx) const { in allUsesAvailableAt()
111 UseIdx = UseIdx.getRegSlot(true); in allUsesAvailableAt()
132 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
135 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
142 SlotIndex UseIdx, bool cheapAsAMove) { in canRematerializeAt() argument
159 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
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| H A D | TargetSchedule.cpp | 175 unsigned UseIdx = 0; in findUseIdx() local
179 ++UseIdx; in findUseIdx()
181 return UseIdx; in findUseIdx()
233 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
234 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
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| H A D | LiveRangeCalc.cpp | 190 SlotIndex UseIdx; in extendToUses() local
195 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); in extendToUses()
207 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber); in extendToUses()
212 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
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| H A D | RegisterCoalescer.cpp | 260 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
798 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef() local
873 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
1560 SlotIndex UseIdx = LIS->getInstructionIndex(MI); in eliminateUndefCopy() local
1568 if (SR.liveAt(UseIdx)) { in eliminateUndefCopy()
1574 isLive = DstLI.liveAt(UseIdx); in eliminateUndefCopy()
1603 if (S.liveAt(UseIdx)) { in addUndefFlag()
1614 LiveQueryResult Q = Int.Query(UseIdx); in addUndefFlag()
1635 addUndefFlag(*DstInt, UseIdx, MO, SubReg); in updateRegDefsUses()
1683 SlotIndex UseIdx = MIIdx.getRegSlot(true); in updateRegDefsUses() local
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| H A D | MachineCopyPropagation.cpp | 215 const MachineInstr &UseI, unsigned UseIdx);
309 unsigned UseIdx) { in isForwardableRegClassCopy() argument
316 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
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| H A D | InlineSpiller.cpp | 527 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
528 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
537 LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI); in reMaterializeFor()
545 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx); in reMaterializeFor()
549 if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) { in reMaterializeFor()
551 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI); in reMaterializeFor()
559 LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI); in reMaterializeFor()
596 LLVM_DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n'); in reMaterializeFor()
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| H A D | MachineVerifier.cpp | 263 SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
1481 unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit, in checkLivenessAtUse() argument
1483 LiveQueryResult LRQ = LR.Query(UseIdx); in checkLivenessAtUse()
1490 report_context(UseIdx); in checkLivenessAtUse()
1498 report_context(UseIdx); in checkLivenessAtUse()
1565 SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness() local
1572 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units); in checkLiveness()
1580 checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg); in checkLiveness()
1591 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask); in checkLiveness()
1592 LiveQueryResult LRQ = SR.Query(UseIdx); in checkLiveness()
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| H A D | TargetInstrInfo.cpp | 1031 SDNode *UseNode, unsigned UseIdx) const { in getOperandLatency()
1042 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1120 unsigned UseIdx) const { in getOperandLatency()
1123 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
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| H A D | MachineCombiner.cpp | 188 int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg()); in getDepth() local
190 InstrPtr, UseIdx); in getDepth()
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| H A D | SplitKit.h | 387 SlotIndex UseIdx,
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 681 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
683 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
684 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
692 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
724 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
726 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) { in recordUnoptimizableWebs()
735 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
736 LLVM_DEBUG(SwapVector[UseIdx].VSEMI->dump()); in recordUnoptimizableWebs()
766 int UseIdx = SwapMap[&UseMI]; in markSwapsForRemoval() local
767 SwapVector[UseIdx].WillRemove = 1; in markSwapsForRemoval()
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| H A D | PPCInstrInfo.h | 220 unsigned UseIdx) const override;
223 SDNode *UseNode, unsigned UseIdx) const override { in getOperandLatency() argument
225 UseNode, UseIdx); in getOperandLatency()
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| H A D | PPCInstrInfo.cpp | 180 unsigned UseIdx) const { in getOperandLatency()
182 UseMI, UseIdx); in getOperandLatency()
1331 unsigned UseIdx; in FoldImmediate() local
1332 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx) in FoldImmediate()
1333 if (UseMI.getOperand(UseIdx).isReg() && in FoldImmediate()
1334 UseMI.getOperand(UseIdx).getReg() == Reg) in FoldImmediate()
1337 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); in FoldImmediate()
1338 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); in FoldImmediate()
1340 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; in FoldImmediate()
1369 UseMI.getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 318 unsigned UseIdx) const override;
321 SDNode *UseNode, unsigned UseIdx) const override;
358 unsigned UseIdx, unsigned UseAlign) const;
362 unsigned UseIdx, unsigned UseAlign) const;
367 unsigned UseIdx, unsigned UseAlign) const;
373 const MachineInstr &UseMI, unsigned UseIdx,
389 unsigned UseIdx) const override;
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| H A D | ARMBaseInstrInfo.cpp | 3635 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3637 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3675 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3677 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
3759 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
3800 UseClass, UseIdx)) in getOperandLatency()
3859 UseIdx = Idx; in getBundledUseMI()
4048 unsigned UseIdx) const { in getOperandLatency()
4111 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) in getOperandLatencyImpl()
4123 UseIdx, UseAlign); in getOperandLatencyImpl()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | LiveRangeEdit.h | 103 SlotIndex UseIdx) const;
213 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx,
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| H A D | TargetInstrInfo.h | 1349 SDNode *UseNode, unsigned UseIdx) const;
1362 unsigned UseIdx) const;
1395 unsigned UseIdx) const { in hasHighOperandLatency() argument
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 351 unsigned UseIdx = -1; in adjustSchedDependency() local
355 UseIdx = OpNum; in adjustSchedDependency()
360 0, *DDst, UseIdx)); in adjustSchedDependency()
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| H A D | HexagonInstrInfo.h | 321 unsigned UseIdx) const override;
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 1127 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
1128 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
1130 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1151 RAEntry.UseIdx = UseIdx; in GenSchedClassTables()
1262 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 643 unsigned UseIdx; in FoldImmediate() local
651 UseIdx = 2; in FoldImmediate()
653 UseIdx = 2, CommuteIdx = 1; in FoldImmediate()
662 UseIdx = 2; in FoldImmediate()
664 UseIdx = 2, CommuteIdx = 1; in FoldImmediate()
673 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx)) in FoldImmediate()
678 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); in FoldImmediate()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1612 SlotIndex UseIdx = LIS->getInstructionIndex(Use); in findReachingDef() local
1625 V = S.getVNInfoAt(UseIdx); in findReachingDef()
1630 V = LI.getVNInfoAt(UseIdx); in findReachingDef()
1639 if (VNInfo *V = LR.getVNInfoAt(UseIdx)) { in findReachingDef()
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