Lines Matching refs:UseIdx
260 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
798 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef() local
799 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
852 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
853 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
873 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
1560 SlotIndex UseIdx = LIS->getInstructionIndex(MI); in eliminateUndefCopy() local
1568 if (SR.liveAt(UseIdx)) { in eliminateUndefCopy()
1574 isLive = DstLI.liveAt(UseIdx); in eliminateUndefCopy()
1578 LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI); in eliminateUndefCopy()
1594 void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx, in addUndefFlag() argument
1603 if (S.liveAt(UseIdx)) { in addUndefFlag()
1614 LiveQueryResult Q = Int.Query(UseIdx); in addUndefFlag()
1634 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true); in updateRegDefsUses() local
1635 addUndefFlag(*DstInt, UseIdx, MO, SubReg); in updateRegDefsUses()
1683 SlotIndex UseIdx = MIIdx.getRegSlot(true); in updateRegDefsUses() local
1684 addUndefFlag(*DstInt, UseIdx, MO, SubIdx); in updateRegDefsUses()