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Searched refs:TargetOpcode (Results 1 – 25 of 190) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp92 case TargetOpcode::G_SDIV: in getRTLibDesc()
95 case TargetOpcode::G_UDIV: in getRTLibDesc()
98 case TargetOpcode::G_SREM: in getRTLibDesc()
101 case TargetOpcode::G_UREM: in getRTLibDesc()
107 case TargetOpcode::G_FADD: in getRTLibDesc()
110 case TargetOpcode::G_FSUB: in getRTLibDesc()
113 case TargetOpcode::G_FMUL: in getRTLibDesc()
116 case TargetOpcode::G_FDIV: in getRTLibDesc()
119 case TargetOpcode::G_FREM: in getRTLibDesc()
123 case TargetOpcode::G_FMA: in getRTLibDesc()
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H A DMachineIRBuilder.cpp350 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
804 case TargetOpcode::G_ADD: in buildInstr()
805 case TargetOpcode::G_AND: in buildInstr()
806 case TargetOpcode::G_ASHR: in buildInstr()
807 case TargetOpcode::G_LSHR: in buildInstr()
808 case TargetOpcode::G_MUL: in buildInstr()
809 case TargetOpcode::G_OR: in buildInstr()
810 case TargetOpcode::G_SHL: in buildInstr()
811 case TargetOpcode::G_SUB: in buildInstr()
812 case TargetOpcode::G_XOR: in buildInstr()
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H A DCombinerHelper.cpp50 if (MI.getOpcode() != TargetOpcode::COPY) in tryCombineCopy()
93 if (OpcodeForCandidate == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
94 CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
97 OpcodeForCandidate != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
104 OpcodeForCandidate == TargetOpcode::G_ZEXT) in ChoosePreferredUse()
173 if (MI.getOpcode() != TargetOpcode::G_LOAD && in tryCombineExtendingLoads()
174 MI.getOpcode() != TargetOpcode::G_SEXTLOAD && in tryCombineExtendingLoads()
175 MI.getOpcode() != TargetOpcode::G_ZEXTLOAD) in tryCombineExtendingLoads()
197 if (UseMI.getOpcode() == TargetOpcode::G_SEXT || in tryCombineExtendingLoads()
198 UseMI.getOpcode() == TargetOpcode::G_ZEXT || in tryCombineExtendingLoads()
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H A DCSEInfo.cpp36 case TargetOpcode::G_ADD: in shouldCSEOpc()
37 case TargetOpcode::G_AND: in shouldCSEOpc()
38 case TargetOpcode::G_ASHR: in shouldCSEOpc()
39 case TargetOpcode::G_LSHR: in shouldCSEOpc()
40 case TargetOpcode::G_MUL: in shouldCSEOpc()
41 case TargetOpcode::G_OR: in shouldCSEOpc()
42 case TargetOpcode::G_SHL: in shouldCSEOpc()
43 case TargetOpcode::G_SUB: in shouldCSEOpc()
44 case TargetOpcode::G_XOR: in shouldCSEOpc()
45 case TargetOpcode::G_UDIV: in shouldCSEOpc()
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H A DUtils.cpp250 case TargetOpcode::G_ADD: in ConstantFoldBinOp()
252 case TargetOpcode::G_AND: in ConstantFoldBinOp()
254 case TargetOpcode::G_ASHR: in ConstantFoldBinOp()
256 case TargetOpcode::G_LSHR: in ConstantFoldBinOp()
258 case TargetOpcode::G_MUL: in ConstantFoldBinOp()
260 case TargetOpcode::G_OR: in ConstantFoldBinOp()
262 case TargetOpcode::G_SHL: in ConstantFoldBinOp()
264 case TargetOpcode::G_SUB: in ConstantFoldBinOp()
266 case TargetOpcode::G_XOR: in ConstantFoldBinOp()
268 case TargetOpcode::G_UDIV: in ConstantFoldBinOp()
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H A DCSEMIRBuilder.cpp144 case TargetOpcode::G_ADD: in buildInstr()
145 case TargetOpcode::G_AND: in buildInstr()
146 case TargetOpcode::G_ASHR: in buildInstr()
147 case TargetOpcode::G_LSHR: in buildInstr()
148 case TargetOpcode::G_MUL: in buildInstr()
149 case TargetOpcode::G_OR: in buildInstr()
150 case TargetOpcode::G_SHL: in buildInstr()
151 case TargetOpcode::G_SUB: in buildInstr()
152 case TargetOpcode::G_XOR: in buildInstr()
153 case TargetOpcode::G_UDIV: in buildInstr()
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H A DLegalizerInfo.cpp114 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegalizerInfo()
115 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegalizerInfo()
116 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegalizerInfo()
117 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegalizerInfo()
118 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegalizerInfo()
120 setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}}); in LegalizerInfo()
126 TargetOpcode::G_ADD, 0, widenToLargerTypesAndNarrowToLargest); in LegalizerInfo()
128 TargetOpcode::G_OR, 0, widenToLargerTypesAndNarrowToLargest); in LegalizerInfo()
130 TargetOpcode::G_LOAD, 0, narrowToSmallerAndUnsupportedIfTooSmall); in LegalizerInfo()
142 setScalarAction(TargetOpcode::G_FNEG, 0, {{1, Lower}}); in LegalizerInfo()
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H A DLegalizer.cpp72 case TargetOpcode::G_TRUNC: in isArtifact()
73 case TargetOpcode::G_ZEXT: in isArtifact()
74 case TargetOpcode::G_ANYEXT: in isArtifact()
75 case TargetOpcode::G_SEXT: in isArtifact()
76 case TargetOpcode::G_MERGE_VALUES: in isArtifact()
77 case TargetOpcode::G_UNMERGE_VALUES: in isArtifact()
78 case TargetOpcode::G_CONCAT_VECTORS: in isArtifact()
79 case TargetOpcode::G_BUILD_VECTOR: in isArtifact()
H A DIRTranslator.cpp345 MIRBuilder.buildInstr(TargetOpcode::G_FNEG) in translateFNeg()
1520 Opcode = TargetOpcode::G_ATOMICRMW_XCHG; in translateAtomicRMW()
1523 Opcode = TargetOpcode::G_ATOMICRMW_ADD; in translateAtomicRMW()
1526 Opcode = TargetOpcode::G_ATOMICRMW_SUB; in translateAtomicRMW()
1529 Opcode = TargetOpcode::G_ATOMICRMW_AND; in translateAtomicRMW()
1532 Opcode = TargetOpcode::G_ATOMICRMW_NAND; in translateAtomicRMW()
1535 Opcode = TargetOpcode::G_ATOMICRMW_OR; in translateAtomicRMW()
1538 Opcode = TargetOpcode::G_ATOMICRMW_XOR; in translateAtomicRMW()
1541 Opcode = TargetOpcode::G_ATOMICRMW_MAX; in translateAtomicRMW()
1544 Opcode = TargetOpcode::G_ATOMICRMW_MIN; in translateAtomicRMW()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h195 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>
207 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>
259 inline UnaryOp_match<SrcTy, TargetOpcode::G_ANYEXT>
266 return UnaryOp_match<SrcTy, TargetOpcode::G_SEXT>(Src);
271 return UnaryOp_match<SrcTy, TargetOpcode::G_ZEXT>(Src);
285 inline UnaryOp_match<SrcTy, TargetOpcode::G_BITCAST>
291 inline UnaryOp_match<SrcTy, TargetOpcode::G_PTRTOINT>
297 inline UnaryOp_match<SrcTy, TargetOpcode::G_INTTOPTR>
303 inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTRUNC>
310 return UnaryOp_match<SrcTy, TargetOpcode::G_FABS>(Src);
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H A DConstantFoldingMIRBuilder.h35 case TargetOpcode::G_ADD:
36 case TargetOpcode::G_AND:
37 case TargetOpcode::G_ASHR:
38 case TargetOpcode::G_LSHR:
39 case TargetOpcode::G_MUL:
40 case TargetOpcode::G_OR:
41 case TargetOpcode::G_SHL:
42 case TargetOpcode::G_SUB:
43 case TargetOpcode::G_XOR:
44 case TargetOpcode::G_UDIV:
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H A DLegalizationArtifactCombiner.h39 if (MI.getOpcode() != TargetOpcode::G_ANYEXT) in tryCombineAnyExt()
72 if (MI.getOpcode() != TargetOpcode::G_ZEXT) in tryCombineZExt()
121 TargetOpcode::G_SHL, {DstTy}, in tryCombineSExt()
134 if (Opcode != TargetOpcode::G_ANYEXT && Opcode != TargetOpcode::G_ZEXT && in tryFoldImplicitDef()
135 Opcode != TargetOpcode::G_SEXT) in tryFoldImplicitDef()
144 if (Opcode == TargetOpcode::G_ANYEXT) { in tryFoldImplicitDef()
260 case TargetOpcode::G_ANYEXT: in tryCombineInstruction()
262 case TargetOpcode::G_ZEXT: in tryCombineInstruction()
264 case TargetOpcode::G_SEXT: in tryCombineInstruction()
266 case TargetOpcode::G_UNMERGE_VALUES: in tryCombineInstruction()
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H A DIRTranslator.h306 return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder); in translateAdd()
309 return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder); in translateSub()
318 return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder); in translateOr()
343 return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder); in translateTrunc()
349 return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder); in translateFPExt()
352 return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder); in translateFPToUI()
355 return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder); in translateFPToSI()
358 return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder); in translateUIToFP()
361 return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder); in translateSIToFP()
367 return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder); in translateSExt()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64RegisterBankInfo.cpp272 case TargetOpcode::G_OR: { in getInstrAlternativeMappings()
368 case TargetOpcode::G_OR: in applyMappingImpl()
370 case TargetOpcode::G_LOAD: in applyMappingImpl()
463 case TargetOpcode::G_ADD: in getInstrMapping()
464 case TargetOpcode::G_SUB: in getInstrMapping()
465 case TargetOpcode::G_GEP: in getInstrMapping()
466 case TargetOpcode::G_MUL: in getInstrMapping()
470 case TargetOpcode::G_AND: in getInstrMapping()
471 case TargetOpcode::G_OR: in getInstrMapping()
472 case TargetOpcode::G_XOR: in getInstrMapping()
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H A DAArch64InstructionSelector.cpp287 case TargetOpcode::G_OR: in selectBinaryOp()
729 if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) { in select()
1029 case TargetOpcode::G_LOAD: in select()
1132 case TargetOpcode::G_FADD: in select()
1133 case TargetOpcode::G_FSUB: in select()
1134 case TargetOpcode::G_FMUL: in select()
1135 case TargetOpcode::G_FDIV: in select()
1137 case TargetOpcode::G_OR: in select()
1138 case TargetOpcode::G_SHL: in select()
1139 case TargetOpcode::G_LSHR: in select()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp174 case TargetOpcode::G_ADD: in getInstrMapping()
175 case TargetOpcode::G_SUB: in getInstrMapping()
176 case TargetOpcode::G_MUL: in getInstrMapping()
177 case TargetOpcode::G_SHL: in getInstrMapping()
178 case TargetOpcode::G_LSHR: in getInstrMapping()
179 case TargetOpcode::G_ASHR: in getInstrMapping()
182 case TargetOpcode::G_FADD: in getInstrMapping()
183 case TargetOpcode::G_FSUB: in getInstrMapping()
184 case TargetOpcode::G_FMUL: in getInstrMapping()
185 case TargetOpcode::G_FDIV: in getInstrMapping()
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H A DX86InstructionSelector.cpp347 case TargetOpcode::G_LOAD: in select()
349 case TargetOpcode::G_GEP: in select()
363 case TargetOpcode::G_ZEXT: in select()
367 case TargetOpcode::G_ICMP: in select()
369 case TargetOpcode::G_FCMP: in select()
385 case TargetOpcode::G_PHI: in select()
387 case TargetOpcode::G_SHL: in select()
388 case TargetOpcode::G_ASHR: in select()
389 case TargetOpcode::G_LSHR: in select()
509 assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) && in selectLoadStoreOp()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DPatchableFunction.cpp46 case TargetOpcode::IMPLICIT_DEF: in doesNotGeneratecode()
47 case TargetOpcode::KILL: in doesNotGeneratecode()
48 case TargetOpcode::CFI_INSTRUCTION: in doesNotGeneratecode()
49 case TargetOpcode::EH_LABEL: in doesNotGeneratecode()
50 case TargetOpcode::GC_LABEL: in doesNotGeneratecode()
51 case TargetOpcode::DBG_VALUE: in doesNotGeneratecode()
52 case TargetOpcode::DBG_LABEL: in doesNotGeneratecode()
74 TII->get(TargetOpcode::PATCHABLE_OP)) in runOnMachineFunction()
H A DExpandPostRAPseudos.cpp99 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
112 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
139 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
214 case TargetOpcode::COPY: in runOnMachineFunction()
217 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
219 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
220 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
H A DDetectDeadLanes.cpp143 case TargetOpcode::COPY: in lowersToCopies()
144 case TargetOpcode::PHI: in lowersToCopies()
145 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
146 case TargetOpcode::REG_SEQUENCE: in lowersToCopies()
147 case TargetOpcode::EXTRACT_SUBREG: in lowersToCopies()
168 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
172 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy()
238 case TargetOpcode::COPY: in transferUsedLanes()
239 case TargetOpcode::PHI: in transferUsedLanes()
340 case TargetOpcode::COPY: in transferDefinedLanes()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstr.h1070 case TargetOpcode::IMPLICIT_DEF:
1071 case TargetOpcode::KILL:
1073 case TargetOpcode::EH_LABEL:
1074 case TargetOpcode::GC_LABEL:
1075 case TargetOpcode::DBG_VALUE:
1076 case TargetOpcode::DBG_LABEL:
1078 case TargetOpcode::LIFETIME_END:
1091 case TargetOpcode::PHI:
1092 case TargetOpcode::G_PHI:
1093 case TargetOpcode::COPY:
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H A DTargetOpcodes.h21 namespace TargetOpcode {
32 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
33 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
38 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp512 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
601 if (Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
806 if (Opc == TargetOpcode::EXTRACT_SUBREG || in EmitMachineNode()
807 Opc == TargetOpcode::INSERT_SUBREG || in EmitMachineNode()
808 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitMachineNode()
814 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { in EmitMachineNode()
820 if (Opc == TargetOpcode::REG_SEQUENCE) { in EmitMachineNode()
825 if (Opc == TargetOpcode::IMPLICIT_DEF) in EmitMachineNode()
835 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) { in EmitMachineNode()
840 if (Opc == TargetOpcode::PATCHPOINT) { in EmitMachineNode()
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H A DResourcePriorityQueue.cpp256 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
257 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
258 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
259 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
260 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
295 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
296 case TargetOpcode::INSERT_SUBREG: in reserveResources()
297 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
298 case TargetOpcode::REG_SEQUENCE: in reserveResources()
299 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp110 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
112 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
113 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
114 case TargetOpcode::COPY: in isResourceAvailable()
115 case TargetOpcode::INLINEASM: in isResourceAvailable()
164 case TargetOpcode::REG_SEQUENCE: in reserveResources()
165 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
166 case TargetOpcode::KILL: in reserveResources()
168 case TargetOpcode::EH_LABEL: in reserveResources()
169 case TargetOpcode::COPY: in reserveResources()
[all …]

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