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Searched refs:SimpleTy (Results 1 – 25 of 62) sorted by relevance

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/freebsd-12.1/contrib/llvm/include/llvm/Support/
H A DMachineValueType.h331 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
337 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
338 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
339 SimpleTy == MVT::v2f16 || SimpleTy == MVT::v1f32); in is32BitVector()
344 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
345 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 || in is64BitVector()
346 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 || in is64BitVector()
347 SimpleTy == MVT::v2f32 || SimpleTy == MVT::v1f64); in is64BitVector()
363 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
390 SimpleTy==MVT::iAny || SimpleTy==MVT::fAny || in isOverloaded()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DValueTypes.h48 if (V.SimpleTy != VT.V.SimpleTy)
50 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
66 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getIntegerVT()
76 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
87 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getVectorVT()
107 assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && in changeVectorElementTypeToInteger()
127 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE; in isSimple()
393 return V.SimpleTy; in getRawBits()
402 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
405 return L.V.SimpleTy < R.V.SimpleTy; in operator()
H A DTargetLowering.h643 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
667 return ValueTypeActions[VT.SimpleTy]; in getTypeAction()
671 ValueTypeActions[VT.SimpleTy] = Action; in setTypeAction()
1054 unsigned Ty = (unsigned)VT.SimpleTy; in getIndexedLoadAction()
1072 unsigned Ty = (unsigned)VT.SimpleTy; in getIndexedStoreAction()
1175 return RegisterTypeForVT[VT.SimpleTy]; in getRegisterType()
1884 RegClassForVT[VT.SimpleTy] = RC; in addRegisterClass()
1913 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift); in setLoadExtAction()
1914 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift; in setLoadExtAction()
1922 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action; in setTruncStoreAction()
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/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1076 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1103 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1320 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1331 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1773 Value.getNode()->getSimpleValueType(0).SimpleTy; in tryStore()
2125 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, in tryLoadParam()
3717 switch (SrcTy.SimpleTy) { in GetConvertOpcode()
3721 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3732 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3743 switch (DestTy.SimpleTy) { in GetConvertOpcode()
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H A DNVPTXTargetTransformInfo.cpp136 if (LT.second.SimpleTy == MVT::i64) in getArithmeticInstrCost()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.h90 if (LocVT.SimpleTy == MVT::i64) in CC_AArch64_Custom_Block()
92 else if (LocVT.SimpleTy == MVT::f16) in CC_AArch64_Custom_Block()
94 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
96 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
98 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
H A DAArch64FastISel.cpp332 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1132 switch (RetVT.SimpleTy) { in emitAddSub()
1151 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1459 switch (VT.SimpleTy) { in emitCmp()
1829 switch (VT.SimpleTy) { in emitLoad()
2060 switch (VT.SimpleTy) { in emitStoreRelease()
2119 switch (VT.SimpleTy) { in emitStore()
2684 switch (VT.SimpleTy) { in selectSelect()
4057 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
4164 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
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/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h92 return (Words[T.SimpleTy / WordWidth] >> (T.SimpleTy % WordWidth)) & 1; in count()
95 bool V = count(T.SimpleTy); in insert()
96 Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth); in insert()
106 Words[T.SimpleTy / WordWidth] &= ~(WordType(1) << (T.SimpleTy % WordWidth)); in erase()
696 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
H A DInfoByHwMode.cpp73 StringRef N = llvm::getEnumName(T.SimpleTy); in getMVTName()
H A DDAGISelMatcherGen.cpp38 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
45 assert((!T.isSimple() || T.getSimple().SimpleTy == VT) && in getRegisterValueType()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FastISel.cpp1930 switch (VT.SimpleTy) { in X86SelectDivRem()
2204 switch (RetVT.SimpleTy) { in X86FastEmitSSESelect()
2301 switch (RetVT.SimpleTy) { in X86FastEmitPseudoSelect()
2697 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2840 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3037 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3149 switch (VT.SimpleTy) { in fastLowerArguments()
3706 switch (VT.SimpleTy) { in X86MaterializeInt()
3728 switch (VT.SimpleTy) { in X86MaterializeInt()
3761 switch (VT.SimpleTy) { in X86MaterializeFP()
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H A DX86ISelDAGToDAG.cpp2630 switch (MemVT.getSimpleVT().SimpleTy) { in foldLoadStoreIntoMemOperand()
3470 switch (NVT.SimpleTy) { in Select()
3519 switch (NVT.SimpleTy) { in Select()
3599 switch (NVT.SimpleTy) { in Select()
3605 switch (NVT.SimpleTy) { in Select()
3690 switch (NVT.SimpleTy) { in Select()
3698 switch (NVT.SimpleTy) { in Select()
3709 switch (NVT.SimpleTy) { in Select()
3766 switch (NVT.SimpleTy) { in Select()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp139 switch (VT.SimpleTy) { in selectIndexedLoad()
181 switch (VT.SimpleTy) { in selectIndexedProgMemLoad()
392 switch (VT.SimpleTy) { in select()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp85 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.cpp133 switch (Ty.SimpleTy) { in toValType()
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp229 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() local
230 switch (SimpleTy) { in LowerFormalArguments()
238 unsigned VReg = RegInfo.createVirtualRegister(SimpleTy == MVT::i64 ? in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp309 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
337 switch (VT.SimpleTy) { in tryIndexedLoad()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DValueTypes.cpp116 switch (V.SimpleTy) { in getEVTString()
203 switch (V.SimpleTy) { in getTypeForEVT()
H A DTargetLoweringBase.cpp409 switch (VT.SimpleTy) { \ in getSYNC()
739 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); in getTypeConversion()
740 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1046 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1267 return getPointerTy(DL).SimpleTy; in getSetCCResultType()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMFastISel.cpp823 switch (VT.SimpleTy) { in ARMSimplifyAddress()
879 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
925 switch (VT.SimpleTy) { in ARMEmitLoad()
1061 switch (VT.SimpleTy) { in ARMEmitStore()
1396 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1839 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1929 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3052 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
H A DARMCallingConv.h207 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
H A DARMISelDAGToDAG.cpp1436 LoadedVT.getSimpleVT().SimpleTy != MVT::i32) in tryT1IndexedLoad()
1471 switch (LoadedVT.getSimpleVT().SimpleTy) { in tryT2IndexedLoad()
1762 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1904 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
2071 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
2190 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
3030 switch (VT.getSimpleVT().SimpleTy) { in Select()
3053 switch (VT.getSimpleVT().SimpleTy) { in Select()
3076 switch (VT.getSimpleVT().SimpleTy) { in Select()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp764 switch (VT.SimpleTy) { in emitLoad()
820 switch (VT.SimpleTy) { in emitStore()
1369 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1830 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1848 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1874 switch (SrcVT.SimpleTy) { in emitIntZExt()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp487 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
490 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp300 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
2134 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandFPLibCall()
2152 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandIntLibCall()
2171 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandDivRemLibCall()
2232 switch (Node->getSimpleValueType(0).SimpleTy) { in isSinCosLibcallAvailable()
2266 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandSinCosLibCall()
2401 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP()
2452 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2493 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
2593 switch (VT.getSimpleVT().getScalarType().SimpleTy) { in ExpandBSWAP()
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