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Searched refs:ShiftVal (Results 1 – 20 of 20) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
268 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
288 ShiftVal = 12; in getAddSubImmOpValue()
290 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
528 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
529 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
534 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
555 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
556 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp73 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
74 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
H A DAArch64FastISel.cpp1229 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1235 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags, in emitAddSub()
1253 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1260 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1615 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1622 RHSIsKill, ShiftVal); in emitLogicalOp()
1632 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1638 RHSIsKill, ShiftVal); in emitLogicalOp()
4644 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4673 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
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H A DAArch64ISelDAGToDAG.cpp348 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
349 if (ShiftVal > 3) in isWorthFoldingSHL()
617 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
624 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
625 if (ShiftVal > 4) in SelectArithExtendedRegister()
653 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
856 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
858 if (ShiftVal != 0 && ShiftVal != LegalShiftVal) in SelectExtendedSHL()
H A DAArch64InstrInfo.cpp772 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
773 if (ShiftVal == 0) in isFalkorShiftExtFast()
775 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
799 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
800 return ShiftVal == 0 || in isFalkorShiftExtFast()
801 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
807 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
808 return ShiftVal == 0 || in isFalkorShiftExtFast()
809 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp982 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
994 if (ShiftVal != 0) in printArithExtend()
995 O << ", lsl #" << ShiftVal; in printArithExtend()
1000 if (ShiftVal != 0) in printArithExtend()
1001 O << " #" << ShiftVal; in printArithExtend()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1168 SDValue ShiftVal = Op.getOperand(1); in UnrollVectorShift() local
1172 DL, ShiftVal.getValueType(), // masked value type in UnrollVectorShift()
1173 ShiftVal, // original shift value operand in UnrollVectorShift()
1174 DAG.getConstant(MaskVal, DL, ShiftVal.getValueType()) // mask operand in UnrollVectorShift()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2013 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2022 ShiftVal = Amount; in isSimpleShift()
2171 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2174 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2175 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2176 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2182 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2185 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2186 (MaskVal << ShiftVal != 0) && in adjustForTestUnderMask()
2187 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal && in adjustForTestUnderMask()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1522 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1529 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
1544 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1545 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
1551 And.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
H A DAMDGPUISelLowering.cpp3956 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
3958 BitsFrom, ShiftVal); in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp464 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
467 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
474 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
H A DInstCombineCompares.cpp1902 const APInt *ShiftVal; in foldICmpShlConstant() local
1903 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
1904 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
2029 const APInt *ShiftVal; in foldICmpShrConstant() local
2030 if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal))) in foldICmpShrConstant()
2031 return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal); in foldICmpShrConstant()
H A DInstCombineCalls.cpp477 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
478 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
484 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
/freebsd-12.1/contrib/llvm/lib/IR/
H A DAutoUpgrade.cpp907 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86ALIGNIntrinsics() local
916 ShiftVal &= (NumElts - 1); in UpgradeX86ALIGNIntrinsics()
920 if (ShiftVal >= 32) in UpgradeX86ALIGNIntrinsics()
925 if (ShiftVal > 16) { in UpgradeX86ALIGNIntrinsics()
926 ShiftVal -= 16; in UpgradeX86ALIGNIntrinsics()
935 unsigned Idx = ShiftVal + i; in UpgradeX86ALIGNIntrinsics()
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGBuiltin.cpp10358 if (ShiftVal >= 32) in EmitX86BuiltinExpr()
10363 if (ShiftVal > 16) { in EmitX86BuiltinExpr()
10364 ShiftVal -= 16; in EmitX86BuiltinExpr()
10373 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
10394 ShiftVal &= (2 * NumElts) - 1; in EmitX86BuiltinExpr()
10398 Indices[i] = i + ShiftVal; in EmitX86BuiltinExpr()
10482 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
10512 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
10540 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
10562 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2559 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
2560 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
H A DX86ISelLowering.cpp6709 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
16450 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
16461 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
30272 if (ShiftVal.uge(VTBits)) in ComputeNumSignBitsForTargetNode()
30275 if (ShiftVal.uge(Tmp)) in ComputeNumSignBitsForTargetNode()
30283 if (ShiftVal.uge(VTBits - 1)) in ComputeNumSignBitsForTargetNode()
30286 ShiftVal += Tmp; in ComputeNumSignBitsForTargetNode()
30287 return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); in ComputeNumSignBitsForTargetNode()
35814 if (ShiftVal >= NumBitsPerElt) { in combineVectorShiftImm()
35822 if (!ShiftVal) in combineVectorShiftImm()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1988 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2004 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DValueTracking.cpp2085 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1); in isKnownNonZero() local
2087 if (Known.countMaxLeadingZeros() < BitWidth - ShiftVal) in isKnownNonZero()
2090 if (Known.countMinTrailingZeros() >= ShiftVal) in isKnownNonZero()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp3434 APInt ShiftVal = C->getAPIntValue(); in ComputeNumSignBits() local
3435 ShiftVal += Tmp; in ComputeNumSignBits()
3436 Tmp = ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); in ComputeNumSignBits()