| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
|
| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
80 // SetCC instructions.
|
| H A D | X86ISelLowering.cpp | 21891 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
21896 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
21902 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
25794 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerADDSUBCARRY()
34585 SDValue SetCC; in checkBoolTestSetCCCombine() local
34591 SetCC = Op2; in checkBoolTestSetCCCombine()
34593 SetCC = Op1; in checkBoolTestSetCCCombine()
34617 SetCC = SetCC.getOperand(OpIdx); in checkBoolTestSetCCCombine()
34620 SetCC = SetCC.getOperand(0); in checkBoolTestSetCCCombine()
38771 return SetCC; in combineXor()
[all …]
|
| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 680 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
682 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
683 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
707 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
710 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
711 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
713 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
736 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
743 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
744 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
[all …]
|
| H A D | MipsSEISelLowering.cpp | 976 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
978 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
982 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
983 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
|
| H A D | MipsInstrInfo.td | 1562 // SetCC
|
| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1966 SDValue SetCC = Z.getOperand(0); in foldAddSubBoolOfMaskedVal() local
1969 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
8272 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
8276 SDValue SOp = SetCC->getOperand(j); in ExtendSetCCUses()
8283 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
8284 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
8480 SDValue SetCC = VSel.getOperand(0); in matchVSelectOpSizesWithSetCC() local
8575 SDValue SetCC = N->getOperand(0); in foldExtendedSignBitTest() local
8577 !SetCC.hasOneUse() || SetCC.getValueType() != MVT::i1) in foldExtendedSignBitTest()
8580 SDValue X = SetCC.getOperand(0); in foldExtendedSignBitTest()
[all …]
|
| H A D | LegalizeIntegerTypes.cpp | 736 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC() local
740 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
|
| H A D | LegalizeDAG.cpp | 3353 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC); in ExpandNode() local
3355 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType)); in ExpandNode()
|
| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3257 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
3259 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
3261 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
3305 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerADDSUBCARRY() local
3307 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerADDSUBCARRY()
3309 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerADDSUBCARRY()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4018 SDNode *SetCC = nullptr; in LowerBRCOND() local
4022 SetCC = Intr; in LowerBRCOND()
4023 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
4047 assert(!SetCC || in LowerBRCOND()
4048 (SetCC->getConstantOperandVal(1) == 1 && in LowerBRCOND()
4049 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == in LowerBRCOND()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11046 SDValue SetCC = in performVSelectCombine() local
11050 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
11107 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); in performSelectCombine() local
11111 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask); in performSelectCombine()
|