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Searched refs:ResVT (Results 1 – 18 of 18) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4516 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4524 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4525 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4560 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4561 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4661 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
4663 if (ResVT.isVector()) { in ReplaceINTRINSIC_W_CHAIN()
4666 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceINTRINSIC_W_CHAIN()
4667 EVT EltVT = ResVT.getVectorElementType(); in ReplaceINTRINSIC_W_CHAIN()
4751 DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceINTRINSIC_W_CHAIN()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1820 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
1858 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags()); in SplitVecOp_VECREDUCE()
1863 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1869 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1875 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
2343 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
2349 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
2355 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
4053 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_SETCC() local
4057 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC, in WidenVecOp_SETCC()
H A DLegalizeIntegerTypes.cpp203 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
205 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
H A DDAGCombiner.cpp5453 EVT ResVT = ExtractFrom.getValueType(); in extractShiftForRotate() local
5455 return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode); in extractShiftForRotate()
13502 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
13503 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
13506 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
13520 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
13526 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2893 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
2900 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
2907 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
2923 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
5116 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
5144 return DAG.getUNDEF(ResVT); in combineExtract()
5174 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
5176 if (VT != ResVT) { in combineExtract()
5178 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
5214 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10049 EVT ResVT = N->getValueType(0); in performExtendCombine() local
10050 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) in performExtendCombine()
10057 if (!ResVT.isSimple() || !SrcVT.isSimple()) in performExtendCombine()
10075 unsigned NumElements = ResVT.getVectorNumElements(); in performExtendCombine()
10091 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
11037 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
11041 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) in performVSelectCombine()
11050 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
11062 EVT ResVT = N->getValueType(0); in performSelectCombine() local
11084 if (!ResVT.isVector() || NumMaskElts == 0) in performSelectCombine()
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H A DAArch64ISelLowering.h383 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DAArch64InstrInfo.td4450 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
4453 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
4457 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
4470 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
4472 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
4476 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.h496 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DARMISelLowering.cpp14463 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
14465 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
14468 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4904 if (ResVT.getVectorElementType() == MVT::i1) in isExtractSubvectorCheap()
9239 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
9241 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
9350 MVT ResVT = Op.getSimpleValueType(); in LowerCONCAT_VECTORSvXi1() local
9406 if (ResVT.getVectorNumElements() >= 16) in LowerCONCAT_VECTORSvXi1()
18440 MVT ResVT = MVT::v4i32; in LowerFP_TO_INT() local
18445 ResVT = MVT::v8i32; in LowerFP_TO_INT()
33640 SAD = DAG.getBitcast(ResVT, SAD); in combineBasicSADPattern()
35107 ResLo = DAG.getBitcast(ResVT, ResLo); in reduceVMULWidth()
35115 ResHi = DAG.getBitcast(ResVT, ResHi); in reduceVMULWidth()
[all …]
H A DX86FastISel.cpp3591 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3592 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3593 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3598 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in fastLowerCall()
H A DX86ISelLowering.h1056 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DX86InstrSSE.td7399 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
7402 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6914 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
6935 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6954 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6968 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6971 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6978 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6984 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
12608 EVT ResVT = Val.getValueType(); in combineStoreFPToInt() local
12611 if (ResVT.getScalarSizeInBits() < 32) in combineStoreFPToInt()
12619 if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() || in combineStoreFPToInt()
[all …]
H A DPPCISelDAGToDAG.cpp4086 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in trySETCC() local
4088 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in trySETCC()
4090 ResVT, VCmp, VCmp); in trySETCC()
4094 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in trySETCC()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2407 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td293 class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
294 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;