4897 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,  in isExtractSubvectorCheap()  argument
4899   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))  in isExtractSubvectorCheap()
4904   if (ResVT.getVectorElementType() == MVT::i1)  in isExtractSubvectorCheap()
4905     return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&  in isExtractSubvectorCheap()
4906                           (Index == ResVT.getVectorNumElements()));  in isExtractSubvectorCheap()
4908   return (Index % ResVT.getVectorNumElements()) == 0;  in isExtractSubvectorCheap()
9239   MVT ResVT = Op.getSimpleValueType();  in LowerAVXCONCAT_VECTORS()  local
9241   assert((ResVT.is256BitVector() ||  in LowerAVXCONCAT_VECTORS()
9242           ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");  in LowerAVXCONCAT_VECTORS()
9263     MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),  in LowerAVXCONCAT_VECTORS()
9264                                   ResVT.getVectorNumElements()/2);  in LowerAVXCONCAT_VECTORS()
9270     return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);  in LowerAVXCONCAT_VECTORS()
9274   SDValue Vec = NumZero ? getZeroVector(ResVT, Subtarget, DAG, dl)  in LowerAVXCONCAT_VECTORS()
9275                         : DAG.getUNDEF(ResVT);  in LowerAVXCONCAT_VECTORS()
9283     Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec,  in LowerAVXCONCAT_VECTORS()
9350   MVT ResVT = Op.getSimpleValueType();  in LowerCONCAT_VECTORSvXi1()  local
9361     return widenSubVector(ResVT, Promoted, true, Subtarget, DAG, dl);  in LowerCONCAT_VECTORSvXi1()
9382     SDValue Vec = NumZero ? getZeroVector(ResVT, Subtarget, DAG, dl)  in LowerCONCAT_VECTORSvXi1()
9383                           : DAG.getUNDEF(ResVT);  in LowerCONCAT_VECTORSvXi1()
9389     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec,  in LowerCONCAT_VECTORSvXi1()
9394     MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),  in LowerCONCAT_VECTORSvXi1()
9395                                   ResVT.getVectorNumElements()/2);  in LowerCONCAT_VECTORSvXi1()
9401     return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);  in LowerCONCAT_VECTORSvXi1()
9406   if (ResVT.getVectorNumElements() >= 16)  in LowerCONCAT_VECTORSvXi1()
9409   SDValue Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT,  in LowerCONCAT_VECTORSvXi1()
9410                             DAG.getUNDEF(ResVT), Op.getOperand(0),  in LowerCONCAT_VECTORSvXi1()
9412   unsigned NumElems = ResVT.getVectorNumElements();  in LowerCONCAT_VECTORSvXi1()
9413   return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(1),  in LowerCONCAT_VECTORSvXi1()
18440       MVT ResVT = MVT::v4i32;  in LowerFP_TO_INT()  local
18445         ResVT = MVT::v8i32;  in LowerFP_TO_INT()
18452       SDValue Res = DAG.getNode(Opc, dl, ResVT, Src);  in LowerFP_TO_INT()
26446         EVT ResVT = getTypeToTransformTo(*DAG.getContext(), VT);  in ReplaceNodeResults()  local
26447         SDValue N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Ops0);  in ReplaceNodeResults()
26448         SDValue N1 = DAG.getConstant(SplatVal, dl, ResVT);  in ReplaceNodeResults()
26449         SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1);  in ReplaceNodeResults()
33553   EVT ResVT = EVT::getIntegerVT(*DAG.getContext(), ResWidth);  in combineHorizontalPredicateResult()  local
33555   SDValue Zero = DAG.getConstant(0, DL, ResVT);  in combineHorizontalPredicateResult()
33556   SDValue Ones = DAG.getAllOnesConstant(DL, ResVT);  in combineHorizontalPredicateResult()
33639   MVT ResVT = MVT::getVectorVT(Type, SadVT.getSizeInBits() / TypeSizeInBits);  in combineBasicSADPattern()  local
33640   SAD = DAG.getBitcast(ResVT, SAD);  in combineBasicSADPattern()
35091     MVT ResVT = MVT::getVectorVT(MVT::i32, NumElts / 2);  in reduceVMULWidth()  local
35107     ResLo = DAG.getBitcast(ResVT, ResLo);  in reduceVMULWidth()
35115     ResHi = DAG.getBitcast(ResVT, ResHi);  in reduceVMULWidth()
35145     MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32);  in reduceVMULWidth()  local
35148                               DL, ResVT, Mul);  in reduceVMULWidth()
35161   MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32);  in reduceVMULWidth()  local
35163   Res = DAG.getBitcast(ResVT, Res);  in reduceVMULWidth()
38535     EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16,  in detectPMADDUBSW()  local
38537     return DAG.getNode(X86ISD::VPMADDUBSW, DL, ResVT, Ops[0], Ops[1]);  in detectPMADDUBSW()
40666     MVT ResVT = MVT::getVectorVT(MVT::i32, Sad.getValueSizeInBits() / 32);  in combineLoopSADPattern()  local
40667     if (VT.getSizeInBits() >= ResVT.getSizeInBits())  in combineLoopSADPattern()
40668       Sad = DAG.getNode(ISD::BITCAST, DL, ResVT, Sad);  in combineLoopSADPattern()
40672     if (VT.getSizeInBits() > ResVT.getSizeInBits()) {  in combineLoopSADPattern()
40819     EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,  in matchPMADDWD()  local
40823     return DAG.getNode(X86ISD::VPMADDWD, DL, ResVT,  in matchPMADDWD()
40978     EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,  in matchPMADDWD_2()  local
40980     return DAG.getNode(X86ISD::VPMADDWD, DL, ResVT, Ops[0], Ops[1]);  in matchPMADDWD_2()