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Searched refs:RecVec (Results 1 – 10 of 10) sorted by relevance

/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp257 const RecVec Defs = in checkSTIPredicates()
601 RecVec SWDefs, SRDefs; in collectSchedRW()
749 RecVec &WriteDefs, RecVec &ReadDefs) { in splitSchedReadWrites()
763 RecVec WriteDefs; in findRWs()
764 RecVec ReadDefs; in findRWs()
1269 const RecVec *InstDefs = Sets.expand(Rec); in inferFromInstRWs()
1665 RecVec Preds; in inferFromTransitions()
1737 RecVec SuperUnits = in hasSuperGroup()
1756 RecVec CheckUnits = in verifyProcResourceGroups()
1761 RecVec OtherUnits = in verifyProcResourceGroups()
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H A DCodeGenSchedule.h32 using RecVec = std::vector<Record*>; variable
55 RecVec Aliases;
99 RecVec PredTerm;
142 RecVec InstRWs;
226 RecVec ItinDefList;
230 RecVec ItinRWDefs;
237 RecVec WriteResDefs;
238 RecVec ReadAdvanceDefs;
241 RecVec ProcResourceDefs;
436 RecVec ProcResourceDefs;
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H A DPredicateExpander.h56 using RecVec = std::vector<Record *>; variable
73 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
74 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
75 void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
87 void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
H A DPredicateExpander.cpp119 const RecVec &Opcodes) { in expandCheckOpcode()
149 const RecVec &Opcodes) { in expandCheckPseudo()
157 const RecVec &Sequence, in expandPredicateSequence()
231 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase()
245 const RecVec &Cases, in expandOpcodeSwitchStatement()
405 RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates"); in expandPrologue()
H A DSubtargetEmitter.cpp209 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
244 RecVec FeatureList = Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
276 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
289 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
336 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
367 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
381 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
606 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResourceSubUnits()
770 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
912 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, in ExpandProcResources()
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H A DInstrInfoEmitter.cpp357 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitMCIIHelperMethods()
406 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitTIIHelperMethods()
H A DRegisterInfoEmitter.cpp1539 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
H A DCodeGenRegisters.cpp750 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
/freebsd-12.1/contrib/llvm/include/llvm/TableGen/
H A DSetTheory.h67 using RecVec = std::vector<Record *>;
98 using ExpandMap = std::map<Record *, RecVec>;
140 const RecVec *expand(Record *Set);
/freebsd-12.1/contrib/llvm/lib/TableGen/
H A DSetTheory.cpp37 using RecVec = SetTheory::RecVec; typedef
231 if (const RecVec *Result = ST.expand(Rec)) in apply()
286 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
309 const RecVec *SetTheory::expand(Record *Set) { in expand()
324 RecVec &EltVec = Expansions[Set]; in expand()