242   const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl");  in checkSTIPredicates()
257   const RecVec Defs =  in checkSTIPredicates()
260     RecVec Opcodes = R->getValueAsListOfDefs("Opcodes");  in checkSTIPredicates()
301     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
307       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
332     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
339       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
408   RecVec RV = Records.getAllDerivedDefinitions("STIPredicate");  in collectSTIPredicates()
444   RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate");  in checkMCInstPredicates()
468   RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit");  in collectRetireControlUnits()
483   RecVec Queues = Records.getAllDerivedDefinitions("MemoryQueue");  in collectLoadStoreQueueInfo()
527   RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");  in collectProcModels()
568 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,  in scanSchedRW()
575     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");  in scanSchedRW()
581     RecVec Vars = RWDef->getValueAsListOfDefs("Variants");  in scanSchedRW()
584       RecVec Selected = Variant->getValueAsListOfDefs("Selected");  in scanSchedRW()
601   RecVec SWDefs, SRDefs;  in collectSchedRW()
606     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");  in collectSchedRW()
617   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedRW()
620     RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
631   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectSchedRW()
634     RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
646   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");  in collectSchedRW()
703       } RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");  in collectSchedRW()
740     RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");  in hasReadOfWrite()
748 static void splitSchedReadWrites(const RecVec &RWDefs,  in splitSchedReadWrites()
749                                  RecVec &WriteDefs, RecVec &ReadDefs) {  in splitSchedReadWrites()
761 void CodeGenSchedModels::findRWs(const RecVec &RWDefs,  in findRWs()
763   RecVec WriteDefs;  in findRWs()
764   RecVec ReadDefs;  in findRWs()
771 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,  in findRWs()
889   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedClasses()
938     const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;  in collectSchedClasses()
996 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {  in createSchedClassName()
1053   const RecVec *InstDefs = Sets.expand(InstRWDef);  in createInstRWClass()
1072       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;  in createInstRWClass()
1074         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);  in createInstRWClass()
1153     RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");  in collectProcItins()
1193   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectProcItinRW()
1249       RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");  in inferFromItinClass()
1269     const RecVec *InstDefs = Sets.expand(Rec);  in inferFromInstRWs()
1364     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in mutuallyExclusive()
1429     const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1449       const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1514     RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");  in pushVariant()
1665     RecVec Preds;  in inferFromTransitions()
1733 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {  in hasSuperGroup()
1737     RecVec SuperUnits =  in hasSuperGroup()
1756     RecVec CheckUnits =  in verifyProcResourceGroups()
1761       RecVec OtherUnits =  in verifyProcResourceGroups()
1782   RecVec RegisterFileDefs = Records.getAllDerivedDefinitions("RegisterFile");  in collectRegisterFiles()
1804     RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");  in collectRegisterFiles()
1849   RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");  in collectProcResources()
1854   RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");  in collectProcResources()
1859   RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");  in collectProcResources()
1864   RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");  in collectProcResources()
1873   RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");  in collectProcResources()
1953       const RecVec &InstRWs = SC.InstRWs;  in checkCompleteness()
1986       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in collectItinProcResources()
2113   RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;  in addWriteRes()
2119   RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");  in addWriteRes()
2129   RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;  in addReadAdvance()