Searched refs:MidVT (Results 1 – 5 of 5) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 4095 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt); in getPromotedVectorElementType() local 4096 assert(TLI.isTypeLegal(MidVT) && "unexpected"); in getPromotedVectorElementType() 4097 return MidVT; in getPromotedVectorElementType() 4399 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local 4432 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local 4433 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode() 4453 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps); in PromoteNode() 4479 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode() 4490 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val); in PromoteNode() 4522 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val); in PromoteNode() [all …]
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| H A D | LegalizeFloatTypes.cpp | 485 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32); in SoftenFloatRes_FP16_TO_FP() local 487 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op, in SoftenFloatRes_FP16_TO_FP()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3146 EVT MidVT = VT.isVector() ? in performTruncateCombine() local 3150 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout()); in performTruncateCombine() 3151 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine() 3160 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9478 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine() local 9479 SmallVector<int, 8> Mask(MidVT.getVectorNumElements()); in performConcatVectorsCombine() 9484 MidVT, dl, in performConcatVectorsCombine() 9485 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine() 9486 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 37111 EVT MidVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16, in combineTruncateWithSat() local 37113 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL, in combineTruncateWithSat()
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