| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 928 switch (getTypeAction(InVT)) { in SplitVecRes_BITCAST()
1180 if (InVT.isVector()) { in SplitVecRes_StrictFPOp()
1867 EVT InVT = Lo.getValueType(); in SplitVecOp_UnaryOp() local
2287 EVT FinalVT = InVT; in SplitVecOp_TruncateHelper()
3057 if (InVT.isVector()) in WidenVecRes_BITCAST()
3064 if (WidenVT.bitsEq(InVT)) in WidenVecRes_BITCAST()
3079 if (WidenVT.bitsEq(InVT)) in WidenVecRes_BITCAST()
3094 if (InVT.isVector()) { in WidenVecRes_BITCAST()
3104 if (InVT.isVector()) { in WidenVecRes_BITCAST()
4486 if (InVT == NVT) in ModifyToType()
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| H A D | LegalizeTypesGeneric.cpp | 45 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST() local
49 switch (getTypeAction(InVT)) { in ExpandRes_BITCAST()
72 if (TLI.hasBigEndianPartOrdering(InVT, DL) != in ExpandRes_BITCAST()
93 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
96 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); in ExpandRes_BITCAST()
106 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
166 SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment); in ExpandRes_BITCAST()
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| H A D | LegalizeIntegerTypes.cpp | 263 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST() local
269 switch (getTypeAction(InVT)) { in PromoteIntRes_BITCAST()
713 EVT InVT = N->getOperand(0).getValueType(); in PromoteIntRes_SETCC() local
716 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
723 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_SETCC()
724 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
817 EVT InVT = InOp.getValueType(); in PromoteIntRes_TRUNCATE() local
818 assert(InVT.isVector() && "Cannot split scalar types"); in PromoteIntRes_TRUNCATE()
819 unsigned NumElts = InVT.getVectorNumElements(); in PromoteIntRes_TRUNCATE()
3636 EVT InVT = InOp0.getValueType(); in PromoteIntRes_EXTRACT_SUBVECTOR() local
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| H A D | SelectionDAG.cpp | 2816 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
2817 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
2820 Known.Zero.setBitsFrom(InVT.getScalarSizeInBits()); in computeKnownBits()
2824 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
2827 Known.Zero.setBitsFrom(InVT.getScalarSizeInBits()); in computeKnownBits()
2831 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
2832 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
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| H A D | DAGCombiner.cpp | 16357 EVT InVT = Vec.getValueType(); in reduceBuildVecToShuffle() local
16370 if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 && in reduceBuildVecToShuffle()
16374 InVT.getVectorElementType(), SplitSize); in reduceBuildVecToShuffle()
16514 EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems); in convertBuildVecZextToZext() local
16517 if (LegalTypes && !TLI.isTypeLegal(InVT)) in convertBuildVecZextToZext()
16527 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
17094 EVT InVT = V.getValueType(); in visitEXTRACT_SUBVECTOR() local
17096 unsigned EltSize = InVT.getScalarSizeInBits(); in visitEXTRACT_SUBVECTOR()
17100 EVT EltVT = InVT.getVectorElementType(); in visitEXTRACT_SUBVECTOR()
17112 Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), InVT, Src); in visitEXTRACT_SUBVECTOR()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 18151 InVT = MVT::i32; in truncateVectorWithPACK()
18157 InVT = EVT::getVectorVT(Ctx, InVT, 128 / InVT.getSizeInBits()); in truncateVectorWithPACK()
18171 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithPACK()
18242 assert((InVT.is256BitVector() || InVT.is128BitVector()) && in LowerTruncateVecI1()
18275 InVT = ExtVT; in LowerTruncateVecI1()
25859 if (InVT == NVT) in ExtendToType()
26533 (InVT == MVT::v16i16 || InVT == MVT::v32i8)) { in ReplaceNodeResults()
26576 (InVT == MVT::v4i16 || InVT == MVT::v4i8)) { in ReplaceNodeResults()
40114 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32) { in combineUIntToFP()
40148 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32) { in combineSIntToFP()
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| H A D | X86InstrAVX512.td | 311 X86VectorVTInfo InVT,
316 !con((ins InVT.RC:$src1), NonTiedIns),
317 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
318 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
320 (vselect InVT.KRCWM:$mask, RHS,
321 (bitconvert InVT.RC:$src1)),
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.h | 269 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) { in MergeInTypeInfo()
270 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
272 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) { in MergeInTypeInfo()
273 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2644 EVT InVT = InputOp.getValueType(); in computeLogicOpInGPR() local
2645 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : in computeLogicOpInGPR()
2646 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
2789 EVT InVT = LHS.getValueType(); in getCompoundZeroComparisonInGPR() local
2790 bool Is32Bit = InVT == MVT::i32; in getCompoundZeroComparisonInGPR()
2798 dl, InVT, LHS, LHS), 0); in getCompoundZeroComparisonInGPR()
4751 EVT InVT = N->getOperand(0).getValueType(); in Select() local
4752 assert((InVT == MVT::i64 || InVT == MVT::i32) && in Select()
4755 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo; in Select()
4756 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, in Select()
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| H A D | PPCISelLowering.cpp | 7357 EVT InVT = Op.getOperand(0).getValueType(); in LowerINT_TO_FP() local
7360 isOperationCustom(Op.getOpcode(), InVT)) in LowerINT_TO_FP()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2892 EVT InVT = In.getValueType(); in lowerBITCAST() local
2907 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
2923 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
3988 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8), in getPermuteNode() local
3990 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0); in getPermuteNode()
3991 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1); in getPermuteNode()
4001 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1); in getPermuteNode()
4710 EVT InVT = PackedOp.getValueType(); in lowerExtendVectorInreg() local
4712 unsigned FromBits = InVT.getScalarSizeInBits(); in lowerExtendVectorInreg()
5355 EVT InVT = VT.changeVectorElementTypeToInteger(); in combineMERGE() local
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2333 EVT InVT = Op.getOperand(0).getValueType(); in LowerVectorFP_TO_INT() local
2335 unsigned NumElts = InVT.getVectorNumElements(); in LowerVectorFP_TO_INT()
2338 if (InVT.getVectorElementType() == MVT::f16) { in LowerVectorFP_TO_INT()
2346 if (VT.getSizeInBits() < InVT.getSizeInBits()) { in LowerVectorFP_TO_INT()
2349 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(), in LowerVectorFP_TO_INT()
2354 if (VT.getSizeInBits() > InVT.getSizeInBits()) { in LowerVectorFP_TO_INT()
2403 EVT InVT = In.getValueType(); in LowerVectorINT_TO_FP() local
2405 if (VT.getSizeInBits() < InVT.getSizeInBits()) { in LowerVectorINT_TO_FP()
2407 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()), in LowerVectorINT_TO_FP()
2408 InVT.getVectorNumElements()); in LowerVectorINT_TO_FP()
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