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Searched refs:GPR64RegClass (Results 1 – 22 of 22) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h49 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
68 const MCRegisterClass *GPR64RegClass; variable
H A DMipsMachineFunction.cpp43 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
60 ? Mips::GPR64RegClass in createEhDataRegsFI()
H A DMipsSERegisterInfo.cpp60 return &Mips::GPR64RegClass; in intRegClass()
226 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
H A DMipsSEInstrInfo.cpp150 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()
151 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
160 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()
262 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
340 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
620 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
H A DMipsSEFrameLowering.cpp423 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
721 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
894 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
911 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
H A DMipsSubtarget.cpp218 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass in getCriticalPathRCs()
H A DMipsRegisterInfo.cpp55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
H A DMipsSEISelLowering.cpp71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
3299 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3485 : &Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3491 unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3537 : &Mips::GPR64RegClass); in emitLD_F16_PSEUDO()
3629 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO()
3733 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPEXTEND_PSEUDO()
H A DMipsSEISelDAGToDAG.cpp152 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
H A DMipsISelLowering.cpp3889 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
3913 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp423 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
481 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
1734 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()
1836 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1850 RC = &AArch64::GPR64RegClass; in emitLoad()
2696 RC = &AArch64::GPR64RegClass; in selectSelect()
3000 RC = &AArch64::GPR64RegClass; in fastLowerArguments()
3249 CallReg = createResultReg(&AArch64::GPR64RegClass); in fastLowerCall()
4813 case MVT::i64: RC = &AArch64::GPR64RegClass; break; in selectBitCast()
4908 RC = &AArch64::GPR64RegClass; in selectSDiv()
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H A DAArch64AdvSIMDScalarPass.cpp110 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
111 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
H A DAArch64CleanupLocalDynamicTLSPass.cpp123 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
H A DAArch64InstrInfo.cpp625 RC = &AArch64::GPR64RegClass; in insertSelect()
2574 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()
3071 SpillRC = &AArch64::GPR64RegClass; in foldMemoryOperandImpl()
4130 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4145 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4171 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4213 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4237 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4263 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4911 for (unsigned Reg : AArch64::GPR64RegClass) { in findRegisterToSaveLRTo()
[all …]
H A DAArch64InstructionSelector.cpp161 : &AArch64::GPR64RegClass; in getRegClassForTypeOnBank()
651 unsigned ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectVaStartDarwin()
680 auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {}); in materializeLargeCMVal()
691 : MRI.createVirtualRegister(&AArch64::GPR64RegClass); in materializeLargeCMVal()
886 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass; in select()
1215 SrcRC == &AArch64::GPR64RegClass) { in select()
1306 MRI.createVirtualRegister(&AArch64::GPR64RegClass); in select()
1612 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues()
H A DAArch64RegisterInfo.cpp253 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass()
486 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
H A DAArch64FrameLowering.cpp379 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister()
1643 if (AArch64::GPR64RegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()
1657 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
1990 if (AArch64::GPR64RegClass.contains(Reg) && in determineCalleeSaves()
2004 if (AArch64::GPR64RegClass.contains(PairedReg) && in determineCalleeSaves()
2067 const TargetRegisterClass &RC = AArch64::GPR64RegClass; in determineCalleeSaves()
H A DAArch64CollectLOH.cpp466 for (MCPhysReg Reg : AArch64::GPR64RegClass) in handleNormalInst()
H A DAArch64FalkorHWPFFix.cpp751 for (unsigned ScratchReg : AArch64::GPR64RegClass) { in runOnLoop()
H A DAArch64LoadStoreOptimizer.cpp941 &AArch64::GPR64RegClass) in promoteLoadFromStore()
H A DAArch64ISelLowering.cpp3087 RC = &AArch64::GPR64RegClass; in LowerFormalArguments()
3259 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); in saveVarArgRegisters()
3960 if (AArch64::GPR64RegClass.contains(*I)) in LowerReturn()
5310 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); in LowerRETURNADDR()
11815 if (AArch64::GPR64RegClass.contains(*I)) in insertCopiesSplitCSR()
11816 RC = &AArch64::GPR64RegClass; in insertCopiesSplitCSR()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp86 GPR64RegClass->contains(CurrentSubReg)) in SetPhysRegUsed()