Lines Matching refs:GPR64RegClass
624 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
625 RC = &AArch64::GPR64RegClass; in insertSelect()
1584 AArch64::GPR64RegClass.contains(DstReg)); in isGPRCopy()
2574 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()
2579 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()
2600 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); in copyPhysReg()
2609 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()
2678 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
2809 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
2982 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
2987 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
3071 SpillRC = &AArch64::GPR64RegClass; in foldMemoryOperandImpl()
4130 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4145 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4171 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4213 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4237 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4263 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
4911 for (unsigned Reg : AArch64::GPR64RegClass) { in findRegisterToSaveLRTo()
5238 for (unsigned Reg : AArch64::GPR64RegClass) { in isMBBSafeToOutlineFrom()