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Searched refs:FSUB (Results 1 – 25 of 46) sorted by relevance

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/freebsd-12.1/bin/pax/
H A Doptions.c101 FSUB fsub[] = {
194 FSUB tmp; in pax_options()
371 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in pax_options()
372 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) { in pax_options()
378 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in pax_options()
1027 FSUB tmp; in cpio_options()
1193 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in cpio_options()
1194 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) in cpio_options()
1198 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in cpio_options()
1306 return(strcmp(((const FSUB *)a)->name, ((const FSUB *)b)->name)); in c_frmt()
H A Dextern.h185 extern FSUB fsub[];
208 extern FSUB *frmt;
H A Dpax.h74 typedef struct fsub FSUB; typedef
H A Dpax.c75 FSUB *frmt = NULL; /* archive format type */
H A Dar_subs.c568 FSUB *orgfrmt; in append()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd in getArithmeticInstrCost()
543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
696 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
697 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
756 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
758 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
759 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
854 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
H A DX86IntrinsicsInfo.h1011 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
1012 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h283 FADD, FSUB, FMUL, FDIV, FREM, enumerator
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp351 case ISD::FSUB: in LegalizeOp()
756 case ISD::FSUB: in Expand()
1147 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG()
1151 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(), in ExpandFNEG()
H A DSelectionDAGBuilder.cpp2685 visitBinary(I, ISD::FSUB); in visitFSub()
4445 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
4599 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4624 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4630 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
4695 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
4721 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
4727 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog2()
4790 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, in expandLog10()
4811 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, in expandLog10()
[all …]
H A DSelectionDAGDumper.cpp244 case ISD::FSUB: return "fsub"; in getOperationName()
H A DLegalizeFloatTypes.cpp104 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult()
1095 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult()
1920 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break; in PromoteFloatResult()
H A DDAGCombiner.cpp741 case ISD::FSUB: in isNegatibleForFree()
792 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
797 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
801 case ISD::FSUB: in GetNegatedExpression()
808 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
1553 case ISD::FSUB: return visitFSUB(N); in visit()
11075 return DAG.getNode(ISD::FSUB, DL, VT, N0, in visitFADD()
11081 return DAG.getNode(ISD::FSUB, DL, VT, N1, in visitFADD()
11095 return DAG.getNode(ISD::FSUB, DL, VT, N1, Add, Flags); in visitFADD()
11101 return DAG.getNode(ISD::FSUB, DL, VT, N0, Add, Flags); in visitFADD()
[all …]
H A DLegalizeDAG.cpp2380 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); in ExpandLegalINT_TO_FP()
3038 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, in ExpandNode()
3129 case ISD::FSUB: { in ExpandNode()
4025 case ISD::FSUB: in ConvertNodeToLibcall()
4325 case ISD::FSUB: in PromoteNode()
H A DTargetLowering.cpp1814 case ISD::FSUB: in SimplifyDemandedVectorElts()
4414 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst)); in expandFP_TO_UINT()
4428 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst)); in expandFP_TO_UINT()
4491 !isOperationLegalOrCustom(ISD::FSUB, DstVT) || in expandUINT_TO_FP()
4513 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52); in expandUINT_TO_FP()
H A DSelectionDAG.cpp3831 case ISD::FSUB: in isKnownNeverNaN()
4434 OpOpcode == ISD::FSUB) in getNode()
4435 return getNode(ISD::FSUB, DL, VT, Operand.getOperand(1), in getNode()
4843 case ISD::FSUB: in getNode()
5115 case ISD::FSUB: in getNode()
5159 case ISD::FSUB: in getNode()
7638 case ISD::STRICT_FSUB: NewOpc = ISD::FSUB; break; in mutateStrictFPToFP()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp389 case ISD::FSUB: in getArithmeticInstrCost()
H A DAMDGPUISelLowering.cpp328 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
465 setOperationAction(ISD::FSUB, VT, Expand); in AMDGPUTargetLowering()
532 setTargetDAGCombine(ISD::FSUB); in AMDGPUTargetLowering()
547 case ISD::FSUB: in fnegFoldsIntoOp()
1970 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); in LowerFREM()
2075 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2110 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND32_16()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td596 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
623 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1127 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
H A DAArch64SchedA57.td429 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
431 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
H A DAArch64SchedKryoDetails.td640 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
670 (instregex "(FADD|FSUB)(D|S)rr")>;
676 (instregex "(FADD|FSUB|FADDP)v2f32")>;
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td41 defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
H A DMipsSEISelLowering.cpp133 setOperationAction(ISD::FSUB, MVT::f16, Promote); in MipsSETargetLowering()
390 setOperationAction(ISD::FSUB, Ty, Legal); in addMSAFloatType()
1885 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td417 (instregex "FSUB(S)?$"),
475 (instregex "FSUB(S)?o$"),
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1421 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1516 setOperationAction(ISD::FSUB, MVT::f64, Expand); in HexagonTargetLowering()
1553 setOperationAction(ISD::FSUB, MVT::f64, Legal); in HexagonTargetLowering()

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